# SN74LVC74AMDREP

**Texas Instruments** · Flip Flops · SOIC-14

SN74LVC74AMDREP from Texas Instruments, in a SOIC-14. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | 1CLR | input | Active-low asynchronous clear for flip-flop 1; a low level resets the outputs regardless of the other inputs. |
| 2 | 1D | input | Data input for flip-flop 1, transferred to the outputs on the positive-going clock edge (setup 3.4 ns min at 3.3 V ± 0.3 V). |
| 3 | 1CLK | input | Positive-edge clock input for flip-flop 1; triggering occurs at a voltage level and is not directly related to the clock rise time. |
| 4 | 1PRE | input | Active-low asynchronous preset for flip-flop 1; a low level sets the outputs regardless of the other inputs. |
| 5 | 1Q | output | True output of flip-flop 1, rated for 24 mA at VCC = 3 V. |
| 6 | 1Q̅ | output | Complementary output of flip-flop 1, rated for 24 mA at VCC = 3 V. |
| 7 | GND | power_in | Ground; continuous current through VCC or GND is limited to ±100 mA. |
| 8 | 2Q̅ | output | Complementary output of flip-flop 2, rated for 24 mA at VCC = 3 V. |
| 9 | 2Q | output | True output of flip-flop 2, rated for 24 mA at VCC = 3 V. |
| 10 | 2PRE | input | Active-low asynchronous preset for flip-flop 2; a low level sets the outputs regardless of the other inputs. |
| 11 | 2CLK | input | Positive-edge clock input for flip-flop 2; triggering occurs at a voltage level and is not directly related to the clock rise time. |
| 12 | 2D | input | Data input for flip-flop 2, transferred to the outputs on the positive-going clock edge (setup 3.4 ns min at 3.3 V ± 0.3 V). |
| 13 | 2CLR | input | Active-low asynchronous clear for flip-flop 2; a low level resets the outputs regardless of the other inputs. |
| 14 | VCC | power_in | Supply voltage, operating range 2 V to 3.6 V (absolute maximum 6.5 V). |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | SOIC-14 |
| Category | Logic |
| Pins | 14 |

## CAD (KiCad official)

- Symbol: `SN74LVC74AMDREP`
- Footprint: `Package_SO:SOIC-14_3.9x8.7mm_P1.27mm`
- 3D model: SOIC-14 (KiCad packages3D, STEP)
- 3D model files: `sn74lvc74amdrep-etched.step` / `sn74lvc74amdrep-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `sn74lvc74amdrep.step` / `sn74lvc74amdrep.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/cn/lit/gpn/sn74lvc74a-ep) (16 pp, sha256 `43b822a559d37a23`, retrieved 2026-10-07, tier: lcsc)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-4-5-20251001` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/sn74lvc74amdrep-datasheet.pdf)