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Contents

Pinout
Key specifications
CAD (KiCad official)
Provenance

README

markdown

SN74LVC573ADWR

Texas Instruments · Latches · SOIC-20-300mil

SN74LVC573ADWR from Texas Instruments, in a SOIC-20-300mil. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	OE	input	Enable pin for the octal transparent D-type latch outputs, listed in the datasheet only as the Enable Pin with no polarity or limits given in this extract.
2	1D	input	Data input 1 to latch 1; the device features state that inputs accept voltages up to 5.5 V.
3	2D	input	Data input 2 to latch 2; inputs accept voltages up to 5.5 V.
4	3D	input	Data input 3 to latch 3; inputs accept voltages up to 5.5 V.
5	4D	input	Data input 4 to latch 4; inputs accept voltages up to 5.5 V.
6	5D	input	Data input 5 to latch 5; inputs accept voltages up to 5.5 V.
7	6D	input	Data input 6 to latch 6; inputs accept voltages up to 5.5 V.
8	7D	input	Data input 7 to latch 7; inputs accept voltages up to 5.5 V.
9	8D	input	Data input 8 to latch 8; inputs accept voltages up to 5.5 V.
10	GND	power_in	Ground pin for the device.
11	LE	input	Latch Enable pin shared by the eight D-type latches; the extract gives only the pin label and function, not the level behavior.
12	8Q	tri_state	Output 8 of the 3-state output stage, designed for driving highly capacitive or relatively low-impedance loads.
13	7Q	tri_state	Output 7 of the 3-state output stage, designed for driving highly capacitive or relatively low-impedance loads.
14	6Q	tri_state	Output 6 of the 3-state output stage, designed for driving highly capacitive or relatively low-impedance loads.
15	5Q	tri_state	Output 5 of the 3-state output stage, designed for driving highly capacitive or relatively low-impedance loads.
16	4Q	tri_state	Output 4 of the 3-state output stage, designed for driving highly capacitive or relatively low-impedance loads.
17	3Q	tri_state	Output 3 of the 3-state output stage, designed for driving highly capacitive or relatively low-impedance loads.
18	2Q	tri_state	Output 2 of the 3-state output stage, designed for driving highly capacitive or relatively low-impedance loads.
19	1Q	tri_state	Output 1 of the 3-state output stage, designed for driving highly capacitive or relatively low-impedance loads.
20	VCC	power_in	Power pin; the SN74LVC573A is designed for 1.65 V to 3.6 V VCC operation.

Key specifications

Parameter	Value
Manufacturer	Texas Instruments
Package	SOIC-20-300mil
Category	Logic
Pins	20

CAD (KiCad official)

Symbol: SN74LVC573ADWR
Footprint: Package_SO:SOIC-20W_7.5x12.8mm_P1.27mm
3D model: SOIC-20-300mil (KiCad packages3D, STEP)
3D model files: sn74lvc573adwr-etched.step / sn74lvc573adwr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); sn74lvc573adwr.step / sn74lvc573adwr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Texas Instruments datasheet (35 pp, sha256 c42a7e40619c1608, retrieved 2026-10-11, tier: lcsc)
Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF