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Contents

README

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SN74LVC541AQDWRQ1

Texas Instruments · Buffers, Drivers, Receivers, Transceivers · SOIC-20-300mil

SN74LVC541AQDWRQ1 from Texas Instruments, in a SOIC-20-300mil. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 OE1 input Output enable 1 input, active low; when high or OE2 is high, all eight outputs (Y1-Y8) are driven to high-impedance state.
2 A1 input Data input A1; accepts 0 to 5.5 V and buffers to output Y1 when both OE1 and OE2 are low.
3 A2 input Data input A2; accepts 0 to 5.5 V and buffers to output Y2 when both OE1 and OE2 are low.
4 A3 input Data input A3; accepts 0 to 5.5 V and buffers to output Y3 when both OE1 and OE2 are low.
5 A4 input Data input A4; accepts 0 to 5.5 V and buffers to output Y4 when both OE1 and OE2 are low.
6 A5 input Data input A5; accepts 0 to 5.5 V and buffers to output Y5 when both OE1 and OE2 are low.
7 A6 input Data input A6; accepts 0 to 5.5 V and buffers to output Y6 when both OE1 and OE2 are low.
8 A7 input Data input A7; accepts 0 to 5.5 V and buffers to output Y7 when both OE1 and OE2 are low.
9 A8 input Data input A8; accepts 0 to 5.5 V and buffers to output Y8 when both OE1 and OE2 are low.
10 GND power_in Ground; negative supply reference.
11 Y8 tri_state 3-state output Y8; buffers input A8 when OE1 and OE2 are low; high-impedance when either output enable is high.
12 Y7 tri_state 3-state output Y7; buffers input A7 when OE1 and OE2 are low; high-impedance when either output enable is high.
13 Y6 tri_state 3-state output Y6; buffers input A6 when OE1 and OE2 are low; high-impedance when either output enable is high.
14 Y5 tri_state 3-state output Y5; buffers input A5 when OE1 and OE2 are low; high-impedance when either output enable is high.
15 Y4 tri_state 3-state output Y4; buffers input A4 when OE1 and OE2 are low; high-impedance when either output enable is high.
16 Y3 tri_state 3-state output Y3; buffers input A3 when OE1 and OE2 are low; high-impedance when either output enable is high.
17 Y2 tri_state 3-state output Y2; buffers input A2 when OE1 and OE2 are low; high-impedance when either output enable is high.
18 Y1 tri_state 3-state output Y1; buffers input A1 when OE1 and OE2 are low; high-impedance when either output enable is high.
19 OE2 input Output enable 2 input, active low; when high or OE1 is high, all eight outputs (Y1-Y8) are driven to high-impedance state.
20 VCC power_in Supply voltage; recommended operating range 2.0 to 3.6 V; inputs tolerate up to 5.5 V.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package SOIC-20-300mil
Category Logic
Pins 20

CAD (KiCad official)

  • Symbol: SN74LVC541AQDWRQ1
  • Footprint: Package_SO:SOIC-20W_7.5x12.8mm_P1.27mm
  • 3D model: SOIC-20-300mil (KiCad packages3D, STEP)
  • 3D model files: sn74lvc541aqdwrq1-etched.step / sn74lvc541aqdwrq1-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); sn74lvc541aqdwrq1.step / sn74lvc541aqdwrq1.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (19 pp, sha256 6a632a4819e239c8, retrieved 2026-09-24, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.2, primary claude-haiku-4-5-20251001 (text), consensus claude-sonnet-4-6 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF