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SN74LVC540AQPWRQ1

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Texas Instruments Logic ICs, TSSOP-20. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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SN74LVC540AQPWRQ1

Texas Instruments · Logic ICs · TSSOP-20

SN74LVC540AQPWRQ1 from Texas Instruments, in a TSSOP-20. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 OE1 input Active-low output enable for the A-to-Y buffers; when OE1 is high, all outputs are forced to the high-impedance state.
2 A1 input Data input to buffer channel 1, which accepts voltages up to 5.5 V.
3 A2 input Data input to buffer channel 2, which accepts voltages up to 5.5 V.
4 A3 input Data input to buffer channel 3, which accepts voltages up to 5.5 V.
5 A4 input Data input to buffer channel 4, which accepts voltages up to 5.5 V.
6 A5 input Data input to buffer channel 5, which accepts voltages up to 5.5 V.
7 A6 input Data input to buffer channel 6, which accepts voltages up to 5.5 V.
8 A7 input Data input to buffer channel 7, which accepts voltages up to 5.5 V.
9 A8 input Data input to buffer channel 8, which accepts voltages up to 5.5 V.
10 GND power_in Ground reference; all unused inputs must be held at VCC or GND for proper device operation.
11 Y8 output 3-state buffer output of channel 8, placed in high impedance when OE1 or OE2 is high.
12 Y7 output 3-state buffer output of channel 7, placed in high impedance when OE1 or OE2 is high.
13 Y6 output 3-state buffer output of channel 6, placed in high impedance when OE1 or OE2 is high.
14 Y5 output 3-state buffer output of channel 5, placed in high impedance when OE1 or OE2 is high.
15 Y4 output 3-state buffer output of channel 4, placed in high impedance when OE1 or OE2 is high.
16 Y3 output 3-state buffer output of channel 3, placed in high impedance when OE1 or OE2 is high.
17 Y2 output 3-state buffer output of channel 2, placed in high impedance when OE1 or OE2 is high.
18 Y1 output 3-state buffer output of channel 1, placed in high impedance when OE1 or OE2 is high.
19 OE2 input Active-low output enable for the A-to-Y buffers; when OE2 is high, all outputs are forced to the high-impedance state.
20 VCC power_in Supply voltage, 2.7 V to 3.6 V for specified operation (2 V to 3.6 V operating range); tie OE to VCC through a pullup resistor to ensure high-impedance during power up or down.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package TSSOP-20
Category Logic ICs
Pins 20

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Operating supply voltage VCC 2 3.6 V Operating 3
Supply voltage, data retention only VCC 1.5 V Data retention only 3
High-level input voltage VIH 2 V VCC = 2.7 V to 3.6 V 3
Low-level input voltage VIL 0.8 V VCC = 2.7 V to 3.6 V 3
Input voltage VI 0 5.5 V 3
Output voltage, 3-state VO 0 5.5 V 3-state 3
High-level output current IOH -12 mA VCC = 2.7 V 3
High-level output current IOH -24 mA VCC = 3 V 3
Low-level output current IOL 12 mA VCC = 2.7 V 3
Low-level output current IOL 24 mA VCC = 3 V 3
Operating free-air temperature TA -40 125 °C 3
Supply voltage range VCC -0.5 6.5 V Over operating free-air temperature range 2
Input voltage range VI -0.5 6.5 V 2
Voltage range applied to any output in the high-impedance or power-off state VO -0.5 6.5 V 2
Voltage range applied to any output in the high or low state VO -0.5 V High or low state; upper limit printed as VCC + 0.5 V 2
Input clamp current IIK -50 mA VI < 0 2
Output clamp current IOK -50 mA VO < 0 2
Continuous output current IO -50 50 mA 2
Continuous current through VCC or GND -100 100 mA 2
Storage temperature range Tstg -65 150 °C 2
Package thermal impedance, PW package θJA 83 °C/W PW package; JESD 51-7 2
High-level output voltage VOH 2.2 V IOH = -12 mA, VCC = 2.7 V 3
High-level output voltage VOH 2.4 V IOH = -12 mA, VCC = 3 V 3
Low-level output voltage VOL 0.2 V IOL = 100 µA, VCC = 2.7 V to 3.6 V 3
Low-level output voltage VOL 0.4 V IOL = 12 mA, VCC = 2.7 V 3
Low-level output voltage VOL 0.55 V IOL = 24 mA, VCC = 3 V 3
Input current II -5 5 µA VI = 0 to 5.5 V, VCC = 3.6 V 3
Off-state output current IOZ -15 15 µA VO = 0 to 5.5 V, VCC = 3.6 V 3
Quiescent supply current ICC 10 µA VI = VCC or GND, IO = 0, VCC = 3.6 V 3
Additional quiescent supply current per input ΔICC 500 µA One input at VCC, 0.6 V, other inputs at VCC or GND; VCC = 2.7 V to 3.6 V 3
Propagation delay, A to Y tpd 1 5.3 ns VCC = 3.3 V ± 0.3 V; see Figure 1 4
Propagation delay, A to Y tpd 7.1 ns VCC = 2.7 V; see Figure 1 4
Enable time, OE to Y ten 1 6.6 ns VCC = 3.3 V ± 0.3 V; see Figure 1 4
Enable time, OE to Y ten 8 ns VCC = 2.7 V; see Figure 1 4
Disable time, OE to Y tdis 1 7.4 ns VCC = 3.3 V ± 0.3 V; see Figure 1 4
Disable time, OE to Y tdis 8.2 ns VCC = 2.7 V; see Figure 1 4

CAD (KiCad official)

  • Symbol: SN74LVC540AQPWRQ1
  • Footprint: Package_SO:TSSOP-20_4.4x6.5mm_P0.65mm
  • 3D model: TSSOP-20 (KiCad packages3D, STEP)
  • 3D model files: sn74lvc540aqpwrq1-etched.step / sn74lvc540aqpwrq1-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); sn74lvc540aqpwrq1.step / sn74lvc540aqpwrq1.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (17 pp, sha256 773273b7a1927d24, retrieved 2026-10-18, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF