# SN74LVC540ADWR

**Texas Instruments** · Buffers, Drivers, Receivers, Transceivers · SOIC-20-300mil

SN74LVC540ADWR from Texas Instruments, in a SOIC-20-300mil. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | OE1 | input | Output Enable 1, active low, enables all outputs when both OE1 and OE2 are low |
| 2 | A1 | input | Channel 1 input, CMOS input accepts 0 to 5.5V |
| 3 | A2 | input | Channel 2 input, CMOS input accepts 0 to 5.5V |
| 4 | A3 | input | Channel 3 input, CMOS input accepts 0 to 5.5V |
| 5 | A4 | input | Channel 4 input, CMOS input accepts 0 to 5.5V |
| 6 | A5 | input | Channel 5 input, CMOS input accepts 0 to 5.5V |
| 7 | A6 | input | Channel 6 input, CMOS input accepts 0 to 5.5V |
| 8 | A7 | input | Channel 7 input, CMOS input accepts 0 to 5.5V |
| 9 | A8 | input | Channel 8 input, CMOS input accepts 0 to 5.5V |
| 10 | GND | power_in | Ground connection, 0V reference |
| 11 | Y8 | output | Channel 8 three-state inverted output, drives 0 to VCC when enabled |
| 12 | Y7 | output | Channel 7 three-state inverted output, drives 0 to VCC when enabled |
| 13 | Y6 | output | Channel 6 three-state inverted output, drives 0 to VCC when enabled |
| 14 | Y5 | output | Channel 5 three-state inverted output, drives 0 to VCC when enabled |
| 15 | Y4 | output | Channel 4 three-state inverted output, drives 0 to VCC when enabled |
| 16 | Y3 | output | Channel 3 three-state inverted output, drives 0 to VCC when enabled |
| 17 | Y2 | output | Channel 2 three-state inverted output, drives 0 to VCC when enabled |
| 18 | Y1 | output | Channel 1 three-state inverted output, drives 0 to VCC when enabled |
| 19 | OE2 | input | Output Enable 2, active low, enables all outputs when both OE1 and OE2 are low |
| 20 | VCC | power_in | Positive power supply, recommended operating range 1.65V to 3.6V |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | SOIC-20-300mil |
| Category | Logic |
| Pins | 20 |

## CAD (KiCad official)

- Symbol: `SN74LVC540ADWR`
- Footprint: `Package_SO:SOIC-20W_7.5x12.8mm_P1.27mm`
- 3D model: SOIC-20-300mil (KiCad packages3D, STEP)
- 3D model files: `sn74lvc540adwr-etched.step` / `sn74lvc540adwr-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `sn74lvc540adwr.step` / `sn74lvc540adwr.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/cn/lit/gpn/sn74lvc540a) (41 pp, sha256 `c6e028cbd21e8c7e`, retrieved 2026-10-05, tier: lcsc)
- **Datasheet language:** Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-4-5-20251001` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/sn74lvc540adwr-datasheet.pdf)