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SN74LVC32AQPWRQ1
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Texas Instruments Logic Gates, TSSOP-14. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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README.mdadded+51@@ -0,0 +1,51 @@+# SN74LVC32AQPWRQ1++**Texas Instruments** · Logic Gates · TSSOP-14++SN74LVC32AQPWRQ1 from Texas Instruments, in a TSSOP-14. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.++## Pinout++| Pin | Name | Type | Function |+|---|---|---|---|+| 1 | 1A | input | Channel 1, Input A; accepts input voltage from 0 to 5.5V for logic high/low determination. |+| 2 | 1B | input | Channel 1, Input B; accepts input voltage from 0 to 5.5V for logic high/low determination. |+| 3 | 1Y | output | Channel 1, Output Y; OR gate output with voltage swing from 0 to VCC. |+| 4 | 2A | input | Channel 2, Input A; accepts input voltage from 0 to 5.5V for logic high/low determination. |+| 5 | 2B | input | Channel 2, Input B; accepts input voltage from 0 to 5.5V for logic high/low determination. |+| 6 | 2Y | output | Channel 2, Output Y; OR gate output with voltage swing from 0 to VCC. |+| 7 | GND | power_in | Ground; 0V reference potential for all logic and power circuits. |+| 8 | 3Y | output | Channel 3, Output Y; OR gate output with voltage swing from 0 to VCC. |+| 9 | 3A | input | Channel 3, Input A; accepts input voltage from 0 to 5.5V for logic high/low determination. |+| 10 | 3B | input | Channel 3, Input B; accepts input voltage from 0 to 5.5V for logic high/low determination. |+| 11 | 4Y | output | Channel 4, Output Y; OR gate output with voltage swing from 0 to VCC. |+| 12 | 4A | input | Channel 4, Input A; accepts input voltage from 0 to 5.5V for logic high/low determination. |+| 13 | 4B | input | Channel 4, Input B; accepts input voltage from 0 to 5.5V for logic high/low determination. |+| 14 | VCC | power_in | Positive supply voltage; 2 to 3.6V operating range with 5.5V input tolerance. |++## Key specifications++| Parameter | Value |+|---|---|+| Manufacturer | Texas Instruments |+| Package | TSSOP-14 |+| Category | Logic |+| Pins | 14 |++## CAD (KiCad official)++- Symbol: `SN74LVC32AQPWRQ1`+- Footprint: `Package_SO:TSSOP-14_4.4x5mm_P0.65mm`+- 3D model: TSSOP-14 (KiCad packages3D, STEP)+- 3D model files: `sn74lvc32aqpwrq1-etched.step` / `sn74lvc32aqpwrq1-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `sn74lvc32aqpwrq1.step` / `sn74lvc32aqpwrq1.glb` are the bare package body.++## Provenance++Data extracted from the manufacturer datasheet, not a distributor listing:++- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/cn/lit/gpn/sn74lvc32a-q1) (25 pp, sha256 `3eaa7b050b5bf4a6`, retrieved 2026-10-07, tier: lcsc)+- **Datasheet language:** Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.+- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-4-5-20251001` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.+- **CAD:** KiCad official libraries (CC-BY-SA 4.0).++[Datasheet PDF](docs/sn74lvc32aqpwrq1-datasheet.pdf)
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accepts input voltage from 0 to 5.5V for logic high/low determination."+ },+ {+ "number": "2",+ "name": "1B",+ "type": "input",+ "description": "Channel 1, Input B; accepts input voltage from 0 to 5.5V for logic high/low determination."+ },+ {+ "number": "3",+ "name": "1Y",+ "type": "output",+ "description": "Channel 1, Output Y; OR gate output with voltage swing from 0 to VCC."+ },+ {+ "number": "4",+ "name": "2A",+ "type": "input",+ "description": "Channel 2, Input A; accepts input voltage from 0 to 5.5V for logic high/low determination."+ },+ {+ "number": "5",+ "name": "2B",+ "type": "input",+ "description": "Channel 2, Input B; accepts input voltage from 0 to 5.5V for logic high/low determination."+ },+ {+ "number": "6",+ "name": "2Y",+ "type": "output",+ "description": "Channel 2, Output Y; OR gate output with voltage swing from 0 to VCC."+ },+ {+ "number": "7",+ "name": "GND",+ "type": "power_in",+ "description": "Ground; 0V reference potential for all logic and power circuits."+ },+ {+ "number": "8",+ "name": "3Y",+ "type": "output",+ "description": "Channel 3, Output Y; OR gate output with voltage swing from 0 to VCC."+ },+ {+ "number": "9",+ "name": "3A",+ "type": "input",+ "description": "Channel 3, Input A; accepts input voltage from 0 to 5.5V for logic high/low determination."+ },+ {+ "number": "10",+ "name": "3B",+ "type": "input",+ "description": "Channel 3, Input B; accepts input voltage from 0 to 5.5V for logic high/low determination."+ },+ {+ "number": "11",+ "name": "4Y",+ "type": "output",+ "description": "Channel 4, Output Y; OR gate output with voltage swing from 0 to VCC."+ },+ {+ "number": "12",+ "name": "4A",+ "type": "input",+ "description": "Channel 4, Input A; accepts input voltage from 0 to 5.5V for logic high/low determination."+ },+ {+ "number": "13",+ "name": "4B",+ "type": "input",+ "description": "Channel 4, Input B; accepts input voltage from 0 to 5.5V for logic high/low determination."+ },+ {+ "number": "14",+ "name": "VCC",+ "type": "power_in",+ "description": "Positive supply voltage; 2 to 3.6V operating range with 5.5V input tolerance."+ }+ ],+ "provenance": {+ "extractor": "extract_pins 0.3",+ "factory_chain": {+ "factory": "2.0.0",+ "extractor": "extract_pins 0.3",+ "primary_model": "claude-haiku-4-5-20251001",+ "primary_mode": "text",+ "consensus_model": "claude-sonnet-5-5",+ "consensus": "agreed",+ "guards": "pin_guards 0.1: passed",+ "guard_notes": [],+ "pages_sent": 25,+ "cost_usd": 0.1116,+ "at": "2026-10-07T07:59:28"+ },+ "datasheet": {+ "url": "https://www.ti.com/cn/lit/gpn/sn74lvc32a-q1",+ "pages": 25,+ "sha256": "3eaa7b050b5bf4a6",+ "source_tier": "lcsc"+ },+ "cad": "KiCad official (CC-BY-SA 4.0)",+ "pins": {+ "total": 14,+ "described": 14,+ "cites_pages": true,+ "refuses_to_fabricate": true+ }+ },+ "viewers": {+ "symbol": "viewers/symbol.html",+ "footprint": "viewers/footprint.html"+ },+ "models_3d": [+ {+ "file": "sn74lvc32aqpwrq1.step",+ "role": "plain",+ "up": "Z",+ "units": "mm",+ "origin": "footprint origin = pad-pattern centre",+ "seat": "z = 0",+ "extents_mm": [+ 6.4,+ 5,+ 1+ ],+ "zmin_mm": 0,+ "centre_offset_mm": 0,+ "footprint_binding": "identity",+ "sha256": "3ee5786aae56190997aa793ba3cfc003fd616782770e29719b4562f012982245",+ "checked": "2026-10-07",+ "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"+ },+ {+ "file": "sn74lvc32aqpwrq1-etched.step",+ "role": "eda",+ "up": "Z",+ "units": "mm",+ "origin": "footprint origin = pad-pattern centre",+ "seat": "z = 0",+ "extents_mm": [+ 6.4,+ 5,+ 1+ ],+ "zmin_mm": 0,+ "centre_offset_mm": 0,+ "footprint_binding": "identity",+ "sha256": "56de2dcc15cf9e8abf3416309bd591e695e5ba6c817b56672c5bfe976cf027ad",+ "checked": "2026-10-07",+ "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"+ }+ ]+ },+ "visibility": "public",+ "org": "adom",+ "author": {+ "name": "Ray",+ "email": "[email protected]"+ }+}