SN74LVC2G74DCUR

{
  "schema_version": 1,
  "type": "component",
  "slug": "sn74lvc2g74dcur",
  "title": "SN74LVC2G74DCUR",
  "brief": "Texas Instruments Flip Flops, VSSOP-8. Pinout extracted from the datasheet, KiCad symbol/footprint/3D.",
  "version": "0.1.0",
  "license": "CC-BY-SA-4.0",
  "tags": [
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    "logic",
    "sn74lvc2g74dcur"
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  "component": {
    "mpn": "SN74LVC2G74DCUR",
    "manufacturer": "Texas Instruments",
    "package": "VSSOP-8",
    "pin_count": 8,
    "category": "Logic",
    "subcategory": "Flip Flops",
    "datasheet": "https://www.ti.com/lit/ds/symlink/sn74lvc2g74dcur.pdf",
    "parts": {
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      "footprint": "sn74lvc2g74dcur.kicad_mod",
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      "model_3d_plain": "sn74lvc2g74dcur.glb",
      "model_3d_step": "sn74lvc2g74dcur-etched.step",
      "model_3d_step_plain": "sn74lvc2g74dcur.step",
      "lbr": "sn74lvc2g74dcur.lbr"
    },
    "distributor_links": {},
    "pins": [
      {
        "number": "1",
        "name": "CLK",
        "type": "input",
        "description": "Clock input. Data at D is transferred to Q on the positive-going edge of CLK when PRE and CLR are inactive (high). Accepts input voltages up to 5.5 V regardless of VCC."
      },
      {
        "number": "2",
        "name": "D",
        "type": "input",
        "description": "Data input. Sampled on the rising edge of CLK and transferred to Q when PRE and CLR are inactive high. Input tolerant to 5.5 V."
      },
      {
        "number": "3",
        "name": "~{Q}",
        "type": "output",
        "description": "Complementary (inverted) flip-flop output. Drives ±24 mA at VCC = 3.3 V. Goes high when the internal Q latch is reset by CLR = L."
      },
      {
        "number": "4",
        "name": "GND",
        "type": "power_in",
        "description": "Ground reference (0 V) for the device."
      },
      {
        "number": "5",
        "name": "Q",
        "type": "output",
        "description": "True flip-flop output. Reflects the state of the D input following the rising edge of CLK. Drives ±24 mA at VCC = 3.3 V."
      },
      {
        "number": "6",
        "name": "~{CLR}",
        "type": "input",
        "description": "Active-low asynchronous clear input. A low level forces Q low regardless of CLK or D. Must be held high for normal clocked operation."
      },
      {
        "number": "7",
        "name": "~{PRE}",
        "type": "input",
        "description": "Active-low asynchronous preset input. A low level forces Q high regardless of CLK or D. Must be held high for normal clocked operation."
      },
      {
        "number": "8",
        "name": "VCC",
        "type": "power_in",
        "description": "Positive supply voltage. Operating range 1.65 V to 5.5 V; data retention down to 1.5 V. Bypass locally with a 0.1 µF ceramic capacitor to GND."
      }
    ],
    "provenance": {
      "extractor": "ds2sf",
      "datasheet": {
        "url": "https://www.ti.com/lit/ds/symlink/sn74lvc2g74dcur.pdf",
        "pages": 18,
        "sha256": "5bb76431d38ce5ae",
        "source_tier": "mfr"
      },
      "cad": "KiCad official (CC-BY-SA 4.0)",
      "pins": {
        "total": 8,
        "described": 8,
        "cites_pages": true,
        "refuses_to_fabricate": true
      }
    },
    "viewers": {
      "symbol": "viewers/symbol.html",
      "footprint": "viewers/footprint.html"
    },
    "logic": {
      "family_id": "74LVC2G74",
      "logic_family": "74LVC",
      "function_code": "2G74",
      "function_class": "Flip-Flop",
      "function_name": "2-gate variant of Dual D Flip-Flop with Set/Reset (74)",
      "manufacturer": "Texas Instruments",
      "is_specialty": false
    },
    "models_3d": [
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        "role": "plain",
        "up": "Z",
        "units": "mm",
        "origin": "footprint origin = pad-pattern centre",
        "seat": "z = 0",
        "extents_mm": [
          3.1,
          2.0,
          0.85
        ],
        "zmin_mm": -0.0,
        "centre_offset_mm": 0.0,
        "footprint_binding": "identity",
        "sha256": "353552981eef35cb93635057d4aeb89aef22648c77af6fd095e328bfe6b834bd",
        "checked": "2026-10-07",
        "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"
      },
      {
        "file": "sn74lvc2g74dcur-etched.step",
        "role": "eda",
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        "units": "mm",
        "origin": "footprint origin = pad-pattern centre",
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        "extents_mm": [
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        "zmin_mm": -0.0,
        "centre_offset_mm": 0.0,
        "footprint_binding": "identity",
        "sha256": "628b5e326b487ef0ab4e81aa29934b07bf4e3070a0cb15b176c63c8cc3ad15fd",
        "checked": "2026-10-07",
        "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"
      }
    ]
  },
  "metadata": {
    "specs": {
      "Manufacturer": "Texas Instruments",
      "Package": "VSSOP-8",
      "Category": "Logic",
      "Pins": "8"
    }
  },
  "sections": [
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    "viewers",
    "readme",
    "breadcrumbs",
    "info"
  ],
  "discovery_triggers": [
    "sn74lvc2g74dcur"
  ],
  "discovery_pitch": "SN74LVC2G74DCUR (Texas Instruments) component page with datasheet-verified CAD.",
  "author": {
    "name": "Ray",
    "email": "[email protected]"
  },
  "dependencies": {},
  "hero": {
    "type": "image",
    "path": "docs/hero.png"
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  "files": [
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  "visibility": {
    "public": true
  },
  "variants": [
    {
      "mpn": "SN74LVC2G74DCUR",
      "kind": "packaging"
    },
    {
      "mpn": "SN74LVC2G74DCURDCUT",
      "kind": "packaging"
    },
    {
      "mpn": "SN74LVC2G74DCURDCTR",
      "kind": "packaging"
    },
    {
      "mpn": "SN74LVC2G74DCURDCTT",
      "kind": "packaging"
    },
    {
      "mpn": "SN74LVC2G74DCURYZPR",
      "kind": "packaging"
    }
  ],
  "updated_at": "2026-09-25T07:45:53.335Z"
}