SN74LVC2G14DBVR

@@ -0,0 +1,46 @@+# SN74LVC2G14DBVR++**UMW** · Inverters · SOT-23-6++SN74LVC2G14DBVR from UMW, in a SOT-23-6. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.++## Pinout++| Pin | Name | Type | Function |+|---|---|---|---|+| 1 | INA1 | input | Schmitt-trigger input to inverter A1. Accepts 0 V to 5.5 V regardless of VCC (over-voltage tolerant). Hysteresis 0.3 V to 1.4 V depending on VCC. |+| 2 | GND | power_in | Ground reference (0 V) for the device. Must be tied to the system ground with a low-inductance path. |+| 3 | INA2 | input | Schmitt-trigger input to inverter A2. Accepts 0 V to 5.5 V regardless of VCC (over-voltage tolerant). Hysteresis 0.3 V to 1.4 V depending on VCC. |+| 4 | Y2 | output | Inverted CMOS push-pull output of channel 2 (Y2 = /INA2). Balanced 24 mA sink/source drive at VCC = 3 V. |+| 5 | VCC | power_in | Positive supply input, 1.65 V to 5.5 V operating range. Decouple with a 0.1 uF ceramic capacitor placed close to the pin. |+| 6 | Y1 | output | Inverted CMOS push-pull output of channel 1 (Y1 = /INA1). Balanced 24 mA sink/source drive at VCC = 3 V. |++## Key specifications++| Parameter | Value |+|---|---|+| Manufacturer | UMW |+| Package | SOT-23-6 |+| Category | Logic |+| Pins | 6 |++## Ordering variants++- `SN74LVC2G14DBVRDBVR`+- `SN74LVC2G14DBVRDCKR`++## CAD (KiCad official)++- Symbol: `SN74LVC2G14DBVR`+- Footprint: `Package_TO_SOT_SMD:SOT-23-6`+- 3D model: SOT-23-6 (KiCad packages3D, STEP)++## Provenance++Data extracted from the manufacturer datasheet, not a distributor listing:++- **Datasheet:** [UMW datasheet](docs/sn74lvc2g14dbvr-datasheet.pdf) (12 pp, sha256 `80e6f9bba73df83b`, retrieved 2026-08-17, tier: lcsc)+- **Extractor:** `ds2sf` (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.+- **CAD:** KiCad official libraries (CC-BY-SA 4.0).++[Datasheet PDF](docs/sn74lvc2g14dbvr-datasheet.pdf)

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