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SN74LVC2G125DCT

Public Made by Adom

by adom

lingxingic Buffers, Drivers, Receivers, Transceivers, TSSOP-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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SN74LVC2G125DCT

lingxingic · Buffers, Drivers, Receivers, Transceivers · TSSOP-8

SN74LVC2G125DCT from lingxingic, in a TSSOP-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 1OE input Active-low output enable for channel 1; when this input is high the 1Y output is forced to the high-impedance (Z) state.
2 1A input Data input for channel 1; recommended input voltage range is 0 V to 5.5 V.
3 2Y tri_state Non-inverting data output for channel 2, which goes to high-impedance when 2OE is high; absolute maximum output current is ±50 mA.
4 GND power_in Ground reference pin at 0 V.
5 2A input Data input for channel 2; recommended input voltage range is 0 V to 5.5 V.
6 1Y tri_state Non-inverting data output for channel 1, which goes to high-impedance when 1OE is high; absolute maximum output current is ±50 mA.
7 2OE input Active-low output enable for channel 2; when this input is high the 2Y output is forced to the high-impedance (Z) state.
8 VCC power_in Supply voltage; recommended range is 1.65 V to 5.5 V, with absolute maximum rating of -0.5 V to +6.5 V.

Key specifications

Parameter Value
Manufacturer lingxingic
Package TSSOP-8
Category Logic
Pins 8

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Supply voltage VCC -0.5 6.5 V 5
Input clamp current IIK -50 mA VI<0V 5
Input voltage VI -0.5 6.5 V 5
Output clamp current IOK -50 50 mA VO>VCC 或 VO<0V 5
Output voltage, enable mode VO -0.5 V 使能模式 5
Output voltage, disable mode VO -0.5 6.5 V 失能模式 5
Output voltage, power-down mode VO -0.5 6.5 V 掉电模式；VCC=0V 5
Output current IO -50 50 mA VO=0V～VCC 5
Supply current ICC 100 mA 5
Ground current IGND -100 mA 5
Storage temperature Tstg -65 150 ℃ 5
Total power dissipation Ptot 300 mW 5
Soldering temperature TL 260 ℃ 10 s 5
Supply voltage VCC 1.65 5.5 V 5
Input voltage VI 0 5.5 V 5
Output voltage, enable mode VO 0 V VCC=1.65V～5.5V；使能模式 5
Output voltage, disable mode VO 0 5.5 V VCC=1.65V～5.5V；失能模式 5
Output voltage, power-down mode VO 0 5.5 V VCC=0V；掉电模式 5
Operating ambient temperature Tamb -40 125 ℃ 5
High-level input voltage VIH 1.7 V VCC=2.3V～2.7V 7
High-level input voltage VIH 2 V VCC=2.7V～3.6V 7
Low-level input voltage VIL 0.7 V VCC=2.3V～2.7V 7
Low-level input voltage VIL 0.8 V VCC=2.7V～3.6V 7
High-level output voltage VOH 0.95 V VI=VIH或VIL；IO=-4mA；VCC=1.65V 7
High-level output voltage VOH 1.7 V VI=VIH或VIL；IO=-8mA；VCC=2.3V 7
High-level output voltage VOH 1.9 V VI=VIH或VIL；IO=-12mA；VCC=2.7V 7
High-level output voltage VOH 2 V VI=VIH或VIL；IO=-24mA；VCC=3.0V 7
High-level output voltage VOH 3.4 V VI=VIH或VIL；IO=-32mA；VCC=4.5V 7
Low-level output voltage VOL 0.1 V VI=VIH或VIL；IO=100uA；VCC=1.65V～5.5V 7
Low-level output voltage VOL 0.7 V VI=VIH或VIL；IO=4mA；VCC=1.65V 7
Low-level output voltage VOL 0.45 V VI=VIH或VIL；IO=8mA；VCC=2.3V 7
Low-level output voltage VOL 0.6 V VI=VIH或VIL；IO=12mA；VCC=2.7V 7
Low-level output voltage VOL 0.8 V VI=VIH或VIL；IO=24mA；VCC=3.0V 7
Input leakage current II -1 1 uA VI=5.5V或GND；VCC=0V～5.5V 7
Off-state output current IOZ -2 2 uA VI=VIH或VIL；VO=5.5V或GND；VCC=3.6V 7
Power-off leakage current IOFF -2 2 uA VI或VO=5.5V；VCC=0V 7
Quiescent supply current ICC 4 uA VI=5.5V或GND；VCC=1.65V～5.5V；IO=0A 7
Additional supply current per input ΔICC 500 uA 每个引脚；VI=VCC-0.6V；IO=0A；VCC=2.3V～5.5V 7
Propagation delay nA to nY tPLH，tPHL 20.9 ns VCC=1.65V～1.95V；见图4 8
Propagation delay nA to nY tPLH，tPHL 14.1 ns VCC=2.3V～2.7V；见图4 8
Propagation delay nA to nY tPLH，tPHL 15.2 ns VCC=2.7V；见图4 8
Propagation delay nA to nY tPLH，tPHL 13.2 ns VCC=3.0V～3.6V；见图4 8
Propagation delay nA to nY tPLH，tPHL 10.6 ns VCC=4.5V～5.5V；见图4 8
Enable time nOE to nY tPZH，tPZL 24.2 ns VCC=1.65V～1.95V；见图5 8
Enable time nOE to nY tPZH，tPZL 15.8 ns VCC=2.3V～2.7V；见图5 8
Enable time nOE to nY tPZH，tPZL 18.5 ns VCC=2.7V；见图5 8
Enable time nOE to nY tPZH，tPZL 13.6 ns VCC=3.0V～3.6V；见图5 8
Enable time nOE to nY tPZH，tPZL 11.4 ns VCC=4.5V～5.5V；见图5 8
Disable time nOE to nY tPLZ，tPHZ 19.1 ns VCC=1.65V～1.95V；见图5 8
Disable time nOE to nY tPLZ，tPHZ 10.6 ns VCC=2.3V～2.7V；见图5 8
Disable time nOE to nY tPLZ，tPHZ 15.7 ns VCC=2.7V；见图5 8
Disable time nOE to nY tPLZ，tPHZ 15.6 ns VCC=3.0V～3.6V；见图5 8
Disable time nOE to nY tPLZ，tPHZ 11 ns VCC=4.5V～5.5V；见图5 8

CAD (KiCad official)

  • Symbol: SN74LVC2G125DCT
  • Footprint: Package_SO:TSSOP-8_3x3mm_P0.65mm
  • 3D model: TSSOP-8 (KiCad packages3D, STEP)
  • 3D model files: sn74lvc2g125dct-etched.step / sn74lvc2g125dct-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); sn74lvc2g125dct.step / sn74lvc2g125dct.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: lingxingic datasheet (13 pp, sha256 2e9223a70cc92a07, retrieved 2026-10-19, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF