component

SN74LVC2G08DCU

Public Made by Adom

by adom

lingxingic Logic Gates, VSSOP-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentlogicsn74lvc2g08dcufactory-2.0.0extractor-text
Overview Files Discover Packages Releases Dependencies Issues Breadcrumbs Pull Requests Activity
main
Download ZIP Propose a change
Generated by kicad-footprint-generator · KiCad file format 20260206
Name Last commit message Last updated
docs Publish 0.1.0 · Ray 5d ago
viewers sn74lvc2g08dcu: viewers · Ray 5d ago
package.json Publish 0.1.0 · Ray 5d ago
page.json Set visibility: public · Ray 5d ago
README.md Publish 0.1.0 · Ray 5d ago
sn74lvc2g08dcu-etched.glb Publish 0.1.0 · Ray 5d ago
sn74lvc2g08dcu-etched.step sn74lvc2g08dcu: factory component page (tier=lcsc) · Ray 5d ago
sn74lvc2g08dcu-hero.glb sn74lvc2g08dcu: hero GLB from the etched model (keeps the MPN mark) · Ray 5d ago
sn74lvc2g08dcu-hero.overlay.json Publish 0.1.0 · Ray 5d ago
sn74lvc2g08dcu.glb Publish 0.1.0 · Ray 5d ago
sn74lvc2g08dcu.kicad_mod Publish 0.1.0 · Ray 5d ago
sn74lvc2g08dcu.kicad_sym Publish 0.1.0 · Ray 5d ago
sn74lvc2g08dcu.lbr Publish 0.1.0 · Ray 5d ago
sn74lvc2g08dcu.step Publish 0.1.0 · Ray 5d ago

SN74LVC2G08DCU

lingxingic · Logic Gates · VSSOP-8

SN74LVC2G08DCU from lingxingic, in a VSSOP-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 1A input Data input 1A of the first AND gate; inputs can be driven from 3.3V or 5V devices, with input voltage range 0 to 5.5V.
2 1B input Data input 1B of the first AND gate; inputs can be driven from 3.3V or 5V devices, with input voltage range 0 to 5.5V.
3 2Y output Data output 2Y of the second AND gate; outputs are 5V tolerant for interfacing with 5V logic.
4 GND power_in Ground (0V) reference for all voltages in the device.
5 2A input Data input 2A of the second AND gate; inputs can be driven from 3.3V or 5V devices, with input voltage range 0 to 5.5V.
6 2B input Data input 2B of the second AND gate; inputs can be driven from 3.3V or 5V devices, with input voltage range 0 to 5.5V.
7 1Y output Data output 1Y of the first AND gate; outputs are 5V tolerant for interfacing with 5V logic.
8 VCC power_in Supply voltage; recommended range 1.65V to 5.5V.

Key specifications

Parameter Value
Manufacturer lingxingic
Package VSSOP-8
Category Logic
Pins 8

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
supply voltage VCC -0.5 6.5 V 5
input voltage VI -0.5 6.5 V 5
output voltage VO -0.5 V Active mode 5
output voltage VO -0.5 6.5 V Power-down mode 5
input clamping current IIK -50 mA VI < 0V 5
output clamping current IOK -50 50 mA VO > VCC or VO < 0V 5
output current IO -50 50 mA VO=0V to VCC 5
supply current ICC 100 mA 5
ground current IGND -100 mA 5
storage temperature Tstg -65 150 ℃ 5
total power dissipation Ptot 300 mW 5
soldering temperature TL 260 ℃ 10s 5
supply voltage VCC 1.65 5.5 V 5
input voltage VI 0 5.5 V 5
output voltage VO 0 V Active mode 5
output voltage VO 0 5.5 V Power-down mode 5
ambient temperature Tamb -40 125 ℃ 5
HIGH-level input voltage VIH 1.7 V Tamb=-40℃ to +125℃; VCC=2.3V to 2.7V 7
HIGH-level input voltage VIH 2 V Tamb=-40℃ to +125℃; VCC=2.7V to 3.6V 7
LOW-level input voltage VIL 0.7 V Tamb=-40℃ to +125℃; VCC=2.3V to 2.7V 7
LOW-level input voltage VIL 0.8 V Tamb=-40℃ to +125℃; VCC=2.7V to 3.6V 7
HIGH-level output voltage VOH 0.95 V Tamb=-40℃ to +125℃; VI = VIH or VIL; IO=-4mA; VCC=1.65V 7
HIGH-level output voltage VOH 1.7 V Tamb=-40℃ to +125℃; VI = VIH or VIL; IO=-8mA; VCC=2.3V 7
HIGH-level output voltage VOH 1.9 V Tamb=-40℃ to +125℃; VI = VIH or VIL; IO=-12mA; VCC=2.7V 7
HIGH-level output voltage VOH 2 V Tamb=-40℃ to +125℃; VI = VIH or VIL; IO=-24mA; VCC=3.0V 7
HIGH-level output voltage VOH 3.4 V Tamb=-40℃ to +125℃; VI = VIH or VIL; IO=-32mA; VCC=4.5V 7
LOW-level output voltage VOL 0.1 V Tamb=-40℃ to +125℃; VI = VIH or VIL; IO=100uA; VCC=1.65V to 5.5V 7
LOW-level output voltage VOL 0.7 V Tamb=-40℃ to +125℃; VI = VIH or VIL; IO=4mA; VCC=1.65V 7
LOW-level output voltage VOL 0.45 V Tamb=-40℃ to +125℃; VI = VIH or VIL; IO=8mA; VCC=2.3V 7
LOW-level output voltage VOL 0.6 V Tamb=-40℃ to +125℃; VI = VIH or VIL; IO=12mA; VCC=2.7V 7
LOW-level output voltage VOL 0.8 V Tamb=-40℃ to +125℃; VI = VIH or VIL; IO=24mA; VCC=3.0V 7
input leakage current II -1 1 uA Tamb=-40℃ to +125℃; VI=5.5V or GND; VCC=0V to 5.5V 7
power-off leakage current IOFF -2 2 uA Tamb=-40℃ to +125℃; VI or VO=5.5V; VCC=0V 7
supply current ICC 4 uA Tamb=-40℃ to +125℃; VI=5.5V or GND; IO=0A; VCC=1.65V to 5.5V 7
additional supply current ΔICC 500 uA Tamb=-40℃ to +125℃; per pin; VI=VCC-0.6V; IO=0A; VCC=2.3V to 5.5V 7
HIGH-level output voltage VOH 1.2 1.53 V Tamb=-40℃ to +85℃; VI = VIH or VIL; IO=-4mA; VCC=1.65V 6
HIGH-level output voltage VOH 1.9 2.13 V Tamb=-40℃ to +85℃; VI = VIH or VIL; IO=-8mA; VCC=2.3V 6
HIGH-level output voltage VOH 2.2 2.5 V Tamb=-40℃ to +85℃; VI = VIH or VIL; IO=-12mA; VCC=2.7V 6
HIGH-level output voltage VOH 2.3 2.6 V Tamb=-40℃ to +85℃; VI = VIH or VIL; IO=-24mA; VCC=3.0V 6
HIGH-level output voltage VOH 3.8 4.1 V Tamb=-40℃ to +85℃; VI = VIH or VIL; IO=-32mA; VCC=4.5V 6
LOW-level output voltage VOL 0.08 0.45 V Tamb=-40℃ to +85℃; VI = VIH or VIL; IO=4mA; VCC=1.65V 6
LOW-level output voltage VOL 0.14 0.3 V Tamb=-40℃ to +85℃; VI = VIH or VIL; IO=8mA; VCC=2.3V 6
LOW-level output voltage VOL 0.19 0.4 V Tamb=-40℃ to +85℃; VI = VIH or VIL; IO=12mA; VCC=2.7V 6
LOW-level output voltage VOL 0.37 0.55 V Tamb=-40℃ to +85℃; VI = VIH or VIL; IO=24mA; VCC=3.0V 6
LOW-level output voltage VOL 0.43 0.55 V Tamb=-40℃ to +85℃; VI = VIH or VIL; IO=32mA; VCC=4.5V 6
LOW-level output voltage VOL 0.1 V Tamb=-40℃ to +85℃; VI = VIH or VIL; IO=100uA; VCC=1.65V to 5.5V 6
nA, nB to nY propagation delay (tPHL) tPHL 20.8 ns Tamb=-40℃ to +125℃; see Figure 5; VCC=1.65V to 1.95V 8
nA, nB to nY propagation delay (tPHL) tPHL 17.8 ns Tamb=-40℃ to +125℃; see Figure 5; VCC=2.3V to 2.7V 8
nA, nB to nY propagation delay (tPHL) tPHL 17 ns Tamb=-40℃ to +125℃; see Figure 5; VCC=2.7V 8
nA, nB to nY propagation delay (tPHL) tPHL 16.3 ns Tamb=-40℃ to +125℃; see Figure 5; VCC=3.0V to 3.6V 8
nA, nB to nY propagation delay (tPHL) tPHL 15.5 ns Tamb=-40℃ to +125℃; see Figure 5; VCC=4.5V to 5.5V 8
nA, nB to nY propagation delay (tPLH) tPLH 23 ns Tamb=-40℃ to +125℃; see Figure 5; VCC=1.65V to 1.95V 8
nA, nB to nY propagation delay (tPLH) tPLH 17 ns Tamb=-40℃ to +125℃; see Figure 5; VCC=2.3V to 2.7V 8
nA, nB to nY propagation delay (tPLH) tPLH 16.3 ns Tamb=-40℃ to +125℃; see Figure 5; VCC=2.7V 8
nA, nB to nY propagation delay (tPLH) tPLH 14.8 ns Tamb=-40℃ to +125℃; see Figure 5; VCC=3.0V to 3.6V 8
nA, nB to nY propagation delay (tPLH) tPLH 13.3 ns Tamb=-40℃ to +125℃; see Figure 5; VCC=4.5V to 5.5V 8

CAD (KiCad official)

  • Symbol: SN74LVC2G08DCU
  • Footprint: Package_SO:VSSOP-8_2.3x2mm_P0.5mm
  • 3D model: VSSOP-8 (KiCad packages3D, STEP)
  • 3D model files: sn74lvc2g08dcu-etched.step / sn74lvc2g08dcu-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); sn74lvc2g08dcu.step / sn74lvc2g08dcu.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: lingxingic datasheet (13 pp, sha256 4e55db036d776e66, retrieved 2026-10-17, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF