SN74LVC2G04DCKR

{
 "schema": "adom.pads/1",
 "slug": "sn74lvc2g04dckr",
 "footprint": "SOT-363_SC-70-6",
 "generated_from": {
  "footprint": "SOT-363_SC-70-6@sha256:0659d885e00b7869",
  "pins": "page.json:component.pins",
  "overrides": null
 },
 "pin1": {
  "pad": "1",
  "at": [
   -0.8375,
   -0.65
  ],
  "corner": "top-left",
  "source": "silk-marker",
  "derived_from": "SOT-363_SC-70-6@sha256:0659d885e00b7869"
 },
 "pad_count": 6,
 "symbol_pins": [
  "1",
  "2",
  "3",
  "4",
  "5",
  "6"
 ],
 "paste_apertures": 0,
 "issues": [],
 "pads": [
  {
   "pad": "1",
   "kind": "smd",
   "shape": "roundrect",
   "at": [
    -0.8375,
    -0.65
   ],
   "rot": 0.0,
   "size": [
    1.025,
    0.35
   ],
   "layers": [
    "F.Cu",
    "F.Mask",
    "F.Paste"
   ],
   "thermal": false,
   "pin": "1",
   "name": "INA1",
   "type": "input",
   "description": "Logic input to inverter gate 1. CMOS input, overvoltage tolerant up to 5.5V independent of VCC. VIH ≥ 0.7·VCC (VCC ≥ 2.3V), VIL ≤ 0.3·VCC. Input leakage ±1 µA max.",
   "is_pin1": true,
   "source": {
    "geometry": "SOT-363_SC-70-6.kicad_mod",
    "meaning": "page.json:component.pins",
    "correspondence": "kicad: symbol pin number == pad name"
   }
  },
  {
   "pad": "2",
   "kind": "smd",
   "shape": "roundrect",
   "at": [
    -0.8375,
    0.0
   ],
   "rot": 0.0,
   "size": [
    1.025,
    0.35
   ],
   "layers": [
    "F.Cu",
    "F.Mask",
    "F.Paste"
   ],
   "thermal": false,
   "pin": "2",
   "name": "GND",
   "type": "power_in",
   "description": "Ground reference (0 V). Common return for VCC and all logic signals.",
   "is_pin1": false,
   "source": {
    "geometry": "SOT-363_SC-70-6.kicad_mod",
    "meaning": "page.json:component.pins",
    "correspondence": "kicad: symbol pin number == pad name"
   }
  },
  {
   "pad": "3",
   "kind": "smd",
   "shape": "roundrect",
   "at": [
    -0.8375,
    0.65
   ],
   "rot": 0.0,
   "size": [
    1.025,
    0.35
   ],
   "layers": [
    "F.Cu",
    "F.Mask",
    "F.Paste"
   ],
   "thermal": false,
   "pin": "3",
   "name": "INA2",
   "type": "input",
   "description": "Logic input to inverter gate 2. CMOS input, overvoltage tolerant up to 5.5V independent of VCC. VIH ≥ 0.7·VCC (VCC ≥ 2.3V), VIL ≤ 0.3·VCC.",
   "is_pin1": false,
   "source": {
    "geometry": "SOT-363_SC-70-6.kicad_mod",
    "meaning": "page.json:component.pins",
    "correspondence": "kicad: symbol pin number == pad name"
   }
  },
  {
   "pad": "4",
   "kind": "smd",
   "shape": "roundrect",
   "at": [
    0.8375,
    0.65
   ],
   "rot": 0.0,
   "size": [
    1.025,
    0.35
   ],
   "layers": [
    "F.Cu",
    "F.Mask",
    "F.Paste"
   ],
   "thermal": false,
   "pin": "4",
   "name": "Y2",
   "type": "output",
   "description": "Inverted logic output of gate 2 (Y2 = /INA2). Push-pull CMOS output with ±24 mA balanced sink/source capability. VOH ≥ VCC−0.1V at 100 µA; VOL ≤ 0.55V at 24 mA (VCC = 3V).",
   "is_pin1": false,
   "source": {
    "geometry": "SOT-363_SC-70-6.kicad_mod",
    "meaning": "page.json:component.pins",
    "correspondence": "kicad: symbol pin number == pad name"
   }
  },
  {
   "pad": "5",
   "kind": "smd",
   "shape": "roundrect",
   "at": [
    0.8375,
    0.0
   ],
   "rot": 0.0,
   "size": [
    1.025,
    0.35
   ],
   "layers": [
    "F.Cu",
    "F.Mask",
    "F.Paste"
   ],
   "thermal": false,
   "pin": "5",
   "name": "VCC",
   "type": "power_in",
   "description": "Positive supply. Operating range 1.65V to 5.5V; absolute maximum 7V. Quiescent supply current ICC ≤ 10 µA. Bypass with a 0.1 µF ceramic capacitor to GND close to the pin.",
   "is_pin1": false,
   "source": {
    "geometry": "SOT-363_SC-70-6.kicad_mod",
    "meaning": "page.json:component.pins",
    "correspondence": "kicad: symbol pin number == pad name"
   }
  },
  {
   "pad": "6",
   "kind": "smd",
   "shape": "roundrect",
   "at": [
    0.8375,
    -0.65
   ],
   "rot": 0.0,
   "size": [
    1.025,
    0.35
   ],
   "layers": [
    "F.Cu",
    "F.Mask",
    "F.Paste"
   ],
   "thermal": false,
   "pin": "6",
   "name": "Y1",
   "type": "output",
   "description": "Inverted logic output of gate 1 (Y1 = /INA1). Push-pull CMOS output with ±24 mA balanced sink/source capability. VOH ≥ VCC−0.1V at 100 µA; VOL ≤ 0.55V at 24 mA (VCC = 3V).",
   "is_pin1": false,
   "source": {
    "geometry": "SOT-363_SC-70-6.kicad_mod",
    "meaning": "page.json:component.pins",
    "correspondence": "kicad: symbol pin number == pad name"
   }
  }
 ]
}