component
SN74LVC2G04DCKR
Public Made by Adomby adom
Texas Instruments Inverters, SOT-363-6. Pinout extracted from the datasheet, KiCad symbol/footprint/3D.
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page.json+9−6@@ -32,7 +32,7 @@ "number": "1", "name": "INA1", "type": "input",- "description": "Logic input to inverter gate 1. CMOS input, overvoltage tolerant up to 5.5V independent of VCC. VIH \u2265 0.7\u00b7VCC (VCC \u2265 2.3V), VIL \u2264 0.3\u00b7VCC. Input leakage \u00b11 \u00b5A max."+ "description": "Logic input to inverter gate 1. CMOS input, overvoltage tolerant up to 5.5V independent of VCC. VIH ≥ 0.7·VCC (VCC ≥ 2.3V), VIL ≤ 0.3·VCC. Input leakage ±1 µA max." }, { "number": "2",@@ -44,25 +44,25 @@ "number": "3", "name": "INA2", "type": "input",- "description": "Logic input to inverter gate 2. CMOS input, overvoltage tolerant up to 5.5V independent of VCC. VIH \u2265 0.7\u00b7VCC (VCC \u2265 2.3V), VIL \u2264 0.3\u00b7VCC."+ "description": "Logic input to inverter gate 2. CMOS input, overvoltage tolerant up to 5.5V independent of VCC. VIH ≥ 0.7·VCC (VCC ≥ 2.3V), VIL ≤ 0.3·VCC." }, { "number": "4", "name": "Y2", "type": "output",- "description": "Inverted logic output of gate 2 (Y2 = /INA2). Push-pull CMOS output with \u00b124 mA balanced sink/source capability. VOH \u2265 VCC\u22120.1V at 100 \u00b5A; VOL \u2264 0.55V at 24 mA (VCC = 3V)."+ "description": "Inverted logic output of gate 2 (Y2 = /INA2). Push-pull CMOS output with ±24 mA balanced sink/source capability. VOH ≥ VCC−0.1V at 100 µA; VOL ≤ 0.55V at 24 mA (VCC = 3V)." }, { "number": "5", "name": "VCC", "type": "power_in",- "description": "Positive supply. Operating range 1.65V to 5.5V; absolute maximum 7V. Quiescent supply current ICC \u2264 10 \u00b5A. Bypass with a 0.1 \u00b5F ceramic capacitor to GND close to the pin."+ "description": "Positive supply. Operating range 1.65V to 5.5V; absolute maximum 7V. Quiescent supply current ICC ≤ 10 µA. Bypass with a 0.1 µF ceramic capacitor to GND close to the pin." }, { "number": "6", "name": "Y1", "type": "output",- "description": "Inverted logic output of gate 1 (Y1 = /INA1). Push-pull CMOS output with \u00b124 mA balanced sink/source capability. VOH \u2265 VCC\u22120.1V at 100 \u00b5A; VOL \u2264 0.55V at 24 mA (VCC = 3V)."+ "description": "Inverted logic output of gate 1 (Y1 = /INA1). Push-pull CMOS output with ±24 mA balanced sink/source capability. VOH ≥ VCC−0.1V at 100 µA; VOL ≤ 0.55V at 24 mA (VCC = 3V)." } ], "provenance": {@@ -126,5 +126,8 @@ "docs/sn74lvc2g04dckr-datasheet.pdf", "viewers/symbol.html", "viewers/footprint.html"- ]+ ],+ "visibility": {+ "public": true+ } }