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Contents

README

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SN74LVC257APWR

Texas Instruments · Signal Switches, Multiplexers, Decoders · TSSOP-16

SN74LVC257APWR from Texas Instruments, in a TSSOP-16. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 A/B input Select input; low selects channel A data, high selects channel B data; rated for 0 to VCC logic levels.
2 1A input Multiplexer input A for output 1Y; accepts input signals from 0 to 5.5 V; input impedance 5 pF.
3 1B input Multiplexer input B for output 1Y; accepts input signals from 0 to 5.5 V; input impedance 5 pF.
4 1Y tri_state Tri-state multiplexer output for channel 1; VOH ≥ VCC − 0.2 V at IOH = −100 μA, VOL ≤ 0.2 V at IOL = 100 μA.
5 2A input Multiplexer input A for output 2Y; accepts input signals from 0 to 5.5 V; input impedance 5 pF.
6 2B input Multiplexer input B for output 2Y; accepts input signals from 0 to 5.5 V; input impedance 5 pF.
7 2Y tri_state Tri-state multiplexer output for channel 2; VOH ≥ VCC − 0.2 V at IOH = −100 μA, VOL ≤ 0.2 V at IOL = 100 μA.
8 GND power_in Ground reference; return path for all device currents.
9 3Y tri_state Tri-state multiplexer output for channel 3; VOH ≥ VCC − 0.2 V at IOH = −100 μA, VOL ≤ 0.2 V at IOL = 100 μA.
10 3B input Multiplexer input B for output 3Y; accepts input signals from 0 to 5.5 V; input impedance 5 pF.
11 3A input Multiplexer input A for output 3Y; accepts input signals from 0 to 5.5 V; input impedance 5 pF.
12 4Y tri_state Tri-state multiplexer output for channel 4; VOH ≥ VCC − 0.2 V at IOH = −100 μA, VOL ≤ 0.2 V at IOL = 100 μA.
13 4B input Multiplexer input B for output 4Y; accepts input signals from 0 to 5.5 V; input impedance 5 pF.
14 4A input Multiplexer input A for output 4Y; accepts input signals from 0 to 5.5 V; input impedance 5 pF.
15 OE input Active-low output enable; when high, all Y outputs enter tri-state; when low, outputs driven; 0 to VCC logic levels.
16 VCC power_in Positive power supply voltage; operating range 1.65 V to 3.6 V; add 0.1 μF bypass capacitor per pin.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package TSSOP-16
Category Logic
Pins 16

CAD (KiCad official)

  • Symbol: SN74LVC257APWR
  • Footprint: Package_SO:TSSOP-16_4.4x5mm_P0.65mm
  • 3D model: TSSOP-16 (KiCad packages3D, STEP)
  • 3D model files: sn74lvc257apwr-etched.step / sn74lvc257apwr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); sn74lvc257apwr.step / sn74lvc257apwr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (39 pp, sha256 79a39fc53062a5a3, retrieved 2026-09-17, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.2, primary claude-haiku-4-5-20251001 (text), consensus claude-sonnet-4-6 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF