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docs sn74lvc245apwr: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray 5d ago
viewers pin 1: carry the footprint's marker into the .lbr, the viewer and page.json (silk-marker, drawn, top-left) · Ray 1mo ago
package.json Publish 0.2.0 · Ray 1mo ago
pads.json pin 1: carry the footprint's marker into the .lbr, the viewer and page.json (silk-marker, drawn, top-left) · Ray 1mo ago
page.json sn74lvc245apwr: component.models_3d pose record per STEP (Z-up, seated z=0, pad-centre origin, identity binding) · Ray 1d ago
README.md sn74lvc245apwr: laser-etched CAD + chip hero (factory 2.0.0 backfill) · Ray 19d ago
sn74lvc245apwr-etched.fit.json sn74lvc245apwr: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray 5d ago
sn74lvc245apwr-etched.glb sn74lvc245apwr: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray 5d ago
sn74lvc245apwr-etched.step sn74lvc245apwr: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray 5d ago
sn74lvc245apwr.glb Publish 0.1.0 · Ray 1mo ago
sn74lvc245apwr.kicad_mod Publish 0.1.0 · Ray 1mo ago
sn74lvc245apwr.kicad_sym Publish 0.1.0 · Ray 1mo ago
sn74lvc245apwr.lbr rebuild the library on adom-lbr 2.32.0. The published copy was built by 2.18.0, which imported every KiCad roundrect and oval pad as a SQUARE EAGLE smd; this carries the real pad shape across (0 -> 20 rounded pads) and stops dropping geometry drawn on KiCad User.N layers. Attributes, connects, pads and the pin-1 marker are gated against decreasing and are unchanged. · Ray 1mo ago
sn74lvc245apwr.step Publish 0.1.0 · Ray 1mo ago

SN74LVC245APWR

Texas Instruments · Buffer/Driver/Transceiver · TSSOP-20

SN74LVC245APWR from Texas Instruments, in a TSSOP-20. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 DIR input Direction control. When high, signal propagates from A port to B port. When low, signal propagates from B port to A port. CMOS logic input referenced to VCC (1.65 V to 3.6 V); accepts up to 5.5 V.
2 A1 tri_state Transceiver I/O pin, channel 1 A-side. Bidirectional 3-state I/O; direction set by DIR, enabled by OE (active-low). IOH up to -24 mA / IOL up to 24 mA at VCC = 3 V.
3 A2 tri_state Transceiver I/O pin, channel 2 A-side. Bidirectional 3-state I/O; direction set by DIR, enabled by OE (active-low).
4 A3 tri_state Transceiver I/O pin, channel 3 A-side. Bidirectional 3-state I/O; direction set by DIR, enabled by OE (active-low).
5 A4 tri_state Transceiver I/O pin, channel 4 A-side. Bidirectional 3-state I/O; direction set by DIR, enabled by OE (active-low).
6 A5 tri_state Transceiver I/O pin, channel 5 A-side. Bidirectional 3-state I/O; direction set by DIR, enabled by OE (active-low).
7 A6 tri_state Transceiver I/O pin, channel 6 A-side. Bidirectional 3-state I/O; direction set by DIR, enabled by OE (active-low).
8 A7 tri_state Transceiver I/O pin, channel 7 A-side. Bidirectional 3-state I/O; direction set by DIR, enabled by OE (active-low).
9 A8 tri_state Transceiver I/O pin, channel 8 A-side. Bidirectional 3-state I/O; direction set by DIR, enabled by OE (active-low).
10 GND power_in Ground reference (0 V). Connect to the system ground plane.
11 B8 tri_state Transceiver I/O pin, channel 8 B-side. Bidirectional 3-state I/O; direction set by DIR, enabled by OE (active-low).
12 B7 tri_state Transceiver I/O pin, channel 7 B-side. Bidirectional 3-state I/O; direction set by DIR, enabled by OE (active-low).
13 B6 tri_state Transceiver I/O pin, channel 6 B-side. Bidirectional 3-state I/O; direction set by DIR, enabled by OE (active-low).
14 B5 tri_state Transceiver I/O pin, channel 5 B-side. Bidirectional 3-state I/O; direction set by DIR, enabled by OE (active-low).
15 B4 tri_state Transceiver I/O pin, channel 4 B-side. Bidirectional 3-state I/O; direction set by DIR, enabled by OE (active-low).
16 B3 tri_state Transceiver I/O pin, channel 3 B-side. Bidirectional 3-state I/O; direction set by DIR, enabled by OE (active-low).
17 B2 tri_state Transceiver I/O pin, channel 2 B-side. Bidirectional 3-state I/O; direction set by DIR, enabled by OE (active-low).
18 B1 tri_state Transceiver I/O pin, channel 1 B-side. Bidirectional 3-state I/O; direction set by DIR, enabled by OE (active-low).
19 OE input Output enable, active-low. When low, all outputs are enabled per DIR. When high, all A and B outputs are placed in the high-impedance (3-state) state. Accepts up to 5.5 V.
20 VCC power_in Supply voltage. Operating range 1.65 V to 3.6 V; absolute maximum 6.5 V. Decouple with ceramic bypass capacitor(s) to GND.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package TSSOP-20
Category Logic
Pins 20

Ordering variants

Same part, different packaging or reel option.

  • SN74LVC245APWR
  • SN74LVC245APWRDB
  • SN74LVC245APWRDGV
  • SN74LVC245APWRDW
  • SN74LVC245APWRN
  • SN74LVC245APWRNS
  • SN74LVC245APWRRGY
  • SN74LVC245APWRGQN
  • SN74LVC245APWRZQN

CAD (KiCad official)

  • Symbol: SN74LVC245APWR
  • Footprint: Package_SO:TSSOP-20_4.4x6.5mm_P0.65mm
  • 3D model: TSSOP-20 (KiCad packages3D, STEP)
  • 3D model files: sn74lvc245apwr-etched.step / sn74lvc245apwr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); sn74lvc245apwr.step / sn74lvc245apwr.glb are the bare package body.

3D model downloads

Two STEP files. Same geometry, different body top:

File Size Use it when
sn74lvc245apwr.step 267 KB You want the bare part, or you mark your own boards.
sn74lvc245apwr-etched.step 2.9 MB You want the part with SN74LVC245APWR already on it.

The marking in the etched file is real recessed geometry cut into the solid, not a texture or a decal: 754 faces against 327 in the bare model. It survives export, section views, and rendering in any CAD tool, and it drops straight into KiCad or Fusion with no extra setup.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (35 pp, sha256 f8c28b30ab2bf1a0, retrieved 2026-08-17, tier: manufacturer)
  • Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF