component
SN74LVC245AIPWREP
Public Made by Adomby adom
Texas Instruments Buffers, Drivers, Receivers, Transceivers, TSSOP-20. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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SN74LVC245AIPWREP
Texas Instruments · Buffers, Drivers, Receivers, Transceivers · TSSOP-20
SN74LVC245AIPWREP from Texas Instruments, in a TSSOP-20. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | DIR | input | Direction-control input: logic low sends B data to the A bus and logic high sends A data to the B bus, per the function table. |
| 2 | A1 | bidirectional | A-bus data pin; inputs accept voltages up to 5.5 V and the Ioff circuitry disables the outputs during partial power-down to prevent backflow. |
| 3 | A2 | bidirectional | A-bus data pin; inputs accept voltages up to 5.5 V and the Ioff circuitry disables the outputs during partial power-down to prevent backflow. |
| 4 | A3 | bidirectional | A-bus data pin; inputs accept voltages up to 5.5 V and the Ioff circuitry disables the outputs during partial power-down to prevent backflow. |
| 5 | A4 | bidirectional | A-bus data pin; inputs accept voltages up to 5.5 V and the Ioff circuitry disables the outputs during partial power-down to prevent backflow. |
| 6 | A5 | bidirectional | A-bus data pin; inputs accept voltages up to 5.5 V and the Ioff circuitry disables the outputs during partial power-down to prevent backflow. |
| 7 | A6 | bidirectional | A-bus data pin; inputs accept voltages up to 5.5 V and the Ioff circuitry disables the outputs during partial power-down to prevent backflow. |
| 8 | A7 | bidirectional | A-bus data pin; inputs accept voltages up to 5.5 V and the Ioff circuitry disables the outputs during partial power-down to prevent backflow. |
| 9 | A8 | bidirectional | A-bus data pin; inputs accept voltages up to 5.5 V and the Ioff circuitry disables the outputs during partial power-down to prevent backflow. |
| 10 | GND | power_in | Ground reference for the device. |
| 11 | B8 | bidirectional | B-bus data pin; inputs accept voltages up to 5.5 V and the Ioff circuitry disables the outputs during partial power-down to prevent backflow. |
| 12 | B7 | bidirectional | B-bus data pin; inputs accept voltages up to 5.5 V and the Ioff circuitry disables the outputs during partial power-down to prevent backflow. |
| 13 | B6 | bidirectional | B-bus data pin; inputs accept voltages up to 5.5 V and the Ioff circuitry disables the outputs during partial power-down to prevent backflow. |
| 14 | B5 | bidirectional | B-bus data pin; inputs accept voltages up to 5.5 V and the Ioff circuitry disables the outputs during partial power-down to prevent backflow. |
| 15 | B4 | bidirectional | B-bus data pin; inputs accept voltages up to 5.5 V and the Ioff circuitry disables the outputs during partial power-down to prevent backflow. |
| 16 | B3 | bidirectional | B-bus data pin; inputs accept voltages up to 5.5 V and the Ioff circuitry disables the outputs during partial power-down to prevent backflow. |
| 17 | B2 | bidirectional | B-bus data pin; inputs accept voltages up to 5.5 V and the Ioff circuitry disables the outputs during partial power-down to prevent backflow. |
| 18 | B1 | bidirectional | B-bus data pin; inputs accept voltages up to 5.5 V and the Ioff circuitry disables the outputs during partial power-down to prevent backflow. |
| 19 | OE | input | Active-low output enable; a high level isolates the A and B buses (high impedance), and it should be tied to VCC through a pullup resistor to hold the high-impedance state during power up or power down. |
| 20 | VCC | power_in | Supply voltage, operating range 1.65 V to 3.6 V. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | TSSOP-20 |
| Category | Logic |
| Pins | 20 |
CAD (KiCad official)
- Symbol:
SN74LVC245AIPWREP - Footprint:
Package_SO:TSSOP-20_4.4x6.5mm_P0.65mm - 3D model: TSSOP-20 (KiCad packages3D, STEP)
- 3D model files:
sn74lvc245aipwrep-etched.step/sn74lvc245aipwrep-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);sn74lvc245aipwrep.step/sn74lvc245aipwrep.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (14 pp, sha256
dfd7d4ae05653670, retrieved 2026-10-11, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# SN74LVC245AIPWREP
**Texas Instruments** · Buffers, Drivers, Receivers, Transceivers · TSSOP-20
SN74LVC245AIPWREP from Texas Instruments, in a TSSOP-20. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | DIR | input | Direction-control input: logic low sends B data to the A bus and logic high sends A data to the B bus, per the function table. |
| 2 | A1 | bidirectional | A-bus data pin; inputs accept voltages up to 5.5 V and the Ioff circuitry disables the outputs during partial power-down to prevent backflow. |
| 3 | A2 | bidirectional | A-bus data pin; inputs accept voltages up to 5.5 V and the Ioff circuitry disables the outputs during partial power-down to prevent backflow. |
| 4 | A3 | bidirectional | A-bus data pin; inputs accept voltages up to 5.5 V and the Ioff circuitry disables the outputs during partial power-down to prevent backflow. |
| 5 | A4 | bidirectional | A-bus data pin; inputs accept voltages up to 5.5 V and the Ioff circuitry disables the outputs during partial power-down to prevent backflow. |
| 6 | A5 | bidirectional | A-bus data pin; inputs accept voltages up to 5.5 V and the Ioff circuitry disables the outputs during partial power-down to prevent backflow. |
| 7 | A6 | bidirectional | A-bus data pin; inputs accept voltages up to 5.5 V and the Ioff circuitry disables the outputs during partial power-down to prevent backflow. |
| 8 | A7 | bidirectional | A-bus data pin; inputs accept voltages up to 5.5 V and the Ioff circuitry disables the outputs during partial power-down to prevent backflow. |
| 9 | A8 | bidirectional | A-bus data pin; inputs accept voltages up to 5.5 V and the Ioff circuitry disables the outputs during partial power-down to prevent backflow. |
| 10 | GND | power_in | Ground reference for the device. |
| 11 | B8 | bidirectional | B-bus data pin; inputs accept voltages up to 5.5 V and the Ioff circuitry disables the outputs during partial power-down to prevent backflow. |
| 12 | B7 | bidirectional | B-bus data pin; inputs accept voltages up to 5.5 V and the Ioff circuitry disables the outputs during partial power-down to prevent backflow. |
| 13 | B6 | bidirectional | B-bus data pin; inputs accept voltages up to 5.5 V and the Ioff circuitry disables the outputs during partial power-down to prevent backflow. |
| 14 | B5 | bidirectional | B-bus data pin; inputs accept voltages up to 5.5 V and the Ioff circuitry disables the outputs during partial power-down to prevent backflow. |
| 15 | B4 | bidirectional | B-bus data pin; inputs accept voltages up to 5.5 V and the Ioff circuitry disables the outputs during partial power-down to prevent backflow. |
| 16 | B3 | bidirectional | B-bus data pin; inputs accept voltages up to 5.5 V and the Ioff circuitry disables the outputs during partial power-down to prevent backflow. |
| 17 | B2 | bidirectional | B-bus data pin; inputs accept voltages up to 5.5 V and the Ioff circuitry disables the outputs during partial power-down to prevent backflow. |
| 18 | B1 | bidirectional | B-bus data pin; inputs accept voltages up to 5.5 V and the Ioff circuitry disables the outputs during partial power-down to prevent backflow. |
| 19 | OE | input | Active-low output enable; a high level isolates the A and B buses (high impedance), and it should be tied to VCC through a pullup resistor to hold the high-impedance state during power up or power down. |
| 20 | VCC | power_in | Supply voltage, operating range 1.65 V to 3.6 V. |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | TSSOP-20 |
| Category | Logic |
| Pins | 20 |
## CAD (KiCad official)
- Symbol: `SN74LVC245AIPWREP`
- Footprint: `Package_SO:TSSOP-20_4.4x6.5mm_P0.65mm`
- 3D model: TSSOP-20 (KiCad packages3D, STEP)
- 3D model files: `sn74lvc245aipwrep-etched.step` / `sn74lvc245aipwrep-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `sn74lvc245aipwrep.step` / `sn74lvc245aipwrep.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/cn/lit/gpn/sn74lvc245a-ep) (14 pp, sha256 `dfd7d4ae05653670`, retrieved 2026-10-11, tier: lcsc)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/sn74lvc245aipwrep-datasheet.pdf)