component

SN74LVC244ADBR

Public Made by Adom

by adom

Texas Instruments Buffer/Driver/Transceiver, SSOP-20-208mil. Pinout extracted from the datasheet, KiCad symbol/footprint/3D.

componentlogicsn74lvc244adbr
Overview Files Discover Packages Releases Dependencies Issues Breadcrumbs Pull Requests Activity
main
Download ZIP Propose a change
Generated by kicad-footprint-generator · KiCad file format 20260206
Name Last commit message Last updated
docs sn74lvc244adbr: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray 5d ago
viewers sn74lvc244adbr: viewers · Ray 29d ago
package.json Publish 0.1.0 · Ray 29d ago
page.json sn74lvc244adbr: component.models_3d pose record per STEP (Z-up, seated z=0, pad-centre origin, identity binding) · Ray 18h ago
README.md sn74lvc244adbr: laser-etched CAD + chip hero (factory 2.0.0 backfill) · Ray 19d ago
sn74lvc244adbr-etched.fit.json sn74lvc244adbr: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray 5d ago
sn74lvc244adbr-etched.glb sn74lvc244adbr: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray 5d ago
sn74lvc244adbr-etched.step sn74lvc244adbr: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray 5d ago
sn74lvc244adbr.glb Publish 0.1.0 · Ray 29d ago
sn74lvc244adbr.kicad_mod Publish 0.1.0 · Ray 29d ago
sn74lvc244adbr.kicad_sym Publish 0.1.0 · Ray 29d ago
sn74lvc244adbr.lbr Publish 0.1.0 · Ray 29d ago
sn74lvc244adbr.step Publish 0.1.0 · Ray 29d ago

SN74LVC244ADBR

Texas Instruments · Buffer/Driver/Transceiver · SSOP-20-208mil

SN74LVC244ADBR from Texas Instruments, in a SSOP-20-208mil. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 1OE input Active-low output enable for the 1Y1-1Y4 bank. When 1OE is low the 1A1-1A4 inputs are driven onto 1Y1-1Y4; when high the 1Y outputs enter the high-impedance (Hi-Z) state.
2 1A1 input Port 1 channel A1 data input. Accepts CMOS logic levels up to 5.5 V independent of VCC (VCC 1.65-3.6 V).
3 2Y4 tri_state Port 2 channel Y4 buffered 3-state output. Follows 2A4 when 2OE is low, Hi-Z when 2OE is high. IOH/IOL up to +/-24 mA at VCC=3 V.
4 1A2 input Port 1 channel A2 data input. Accepts CMOS logic levels up to 5.5 V independent of VCC.
5 2Y3 tri_state Port 2 channel Y3 buffered 3-state output. Follows 2A3 when 2OE is low, Hi-Z when 2OE is high.
6 1A3 input Port 1 channel A3 data input. Accepts CMOS logic levels up to 5.5 V.
7 2Y2 tri_state Port 2 channel Y2 buffered 3-state output. Follows 2A2 when 2OE is low, Hi-Z when 2OE is high.
8 1A4 input Port 1 channel A4 data input. Accepts CMOS logic levels up to 5.5 V.
9 2Y1 tri_state Port 2 channel Y1 buffered 3-state output. Follows 2A1 when 2OE is low, Hi-Z when 2OE is high.
10 GND power_in Ground reference (0 V).
11 2A1 input Port 2 channel A1 data input. Accepts CMOS logic levels up to 5.5 V.
12 1Y4 tri_state Port 1 channel Y4 buffered 3-state output. Follows 1A4 when 1OE is low, Hi-Z when 1OE is high.
13 2A2 input Port 2 channel A2 data input. Accepts CMOS logic levels up to 5.5 V.
14 1Y3 tri_state Port 1 channel Y3 buffered 3-state output. Follows 1A3 when 1OE is low, Hi-Z when 1OE is high.
15 2A3 input Port 2 channel A3 data input. Accepts CMOS logic levels up to 5.5 V.
16 1Y2 tri_state Port 1 channel Y2 buffered 3-state output. Follows 1A2 when 1OE is low, Hi-Z when 1OE is high.
17 2A4 input Port 2 channel A4 data input. Accepts CMOS logic levels up to 5.5 V.
18 1Y1 tri_state Port 1 channel Y1 buffered 3-state output. Follows 1A1 when 1OE is low, Hi-Z when 1OE is high.
19 2OE input Active-low output enable for the 2Y1-2Y4 bank. When 2OE is low the 2A1-2A4 inputs are driven onto 2Y1-2Y4; when high the 2Y outputs enter Hi-Z.
20 VCC power_in Supply voltage. Operating range 1.65 V to 3.6 V (data retention >=1.5 V). Absolute maximum 6.5 V.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package SSOP-20-208mil
Category Logic
Pins 20

Ordering variants

Same part, different packaging or reel option.

  • SN74LVC244ADBR
  • SN74LVC244ADBRAN
  • SN74LVC244ADBRANS
  • SN74LVC244ADBRADGV
  • SN74LVC244ADBRADW
  • SN74LVC244ADBRARGY
  • SN74LVC244ADBRAZQN
  • SN74LVC244ADBRAPW
  • SN74LVC244ADBRARWP

CAD (KiCad official)

  • Symbol: SN74LVC244ADBR
  • Footprint: Package_SO:SSOP-20_5.3x7.2mm_P0.65mm
  • 3D model: SSOP-20-208mil (KiCad packages3D, STEP)
  • 3D model files: sn74lvc244adbr-etched.step / sn74lvc244adbr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); sn74lvc244adbr.step / sn74lvc244adbr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (36 pp, sha256 6fe0efecbb5e363d, retrieved 2026-08-17, tier: manufacturer)
  • Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF