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sn74lvc244adbr: factory component page (tier=mfr)

Ray ·562c8fd518 ·29d ago ·parent c2eadce
1 file changed +226−8
page.json+226−8
@@ -1,13 +1,236 @@ {+  "schema_version": 1,+  "type": "component",   "slug": "sn74lvc244adbr",+  "title": "SN74LVC244ADBR",+  "brief": "Texas Instruments Buffer/Driver/Transceiver, SSOP-20-208mil. Datasheet-verified pinout, KiCad symbol/footprint/3D.",   "version": "0.1.0",-  "type": "component",-  "description": "Texas Instruments Buffer/Driver/Transceiver, SSOP-20-208mil. Datasheet-verified pinout, KiCad symbol/footprint/3D.",+  "license": "CC-BY-SA-4.0",   "tags": [     "component",     "logic",     "sn74lvc244adbr"   ],+  "component": {+    "mpn": "SN74LVC244ADBR",+    "manufacturer": "Texas Instruments",+    "package": "SSOP-20-208mil",+    "pin_count": 20,+    "category": "Logic",+    "subcategory": "Buffer/Driver/Transceiver",+    "datasheet": "https://www.ti.com/lit/ds/symlink/sn74lvc244adbr.pdf",+    "parts": {+      "symbol": "sn74lvc244adbr.kicad_sym",+      "footprint": "sn74lvc244adbr.kicad_mod",+      "model_3d": "sn74lvc244adbr.glb",+      "model_3d_step": "sn74lvc244adbr.step",+      "lbr": "sn74lvc244adbr.lbr"+    },+    "distributor_links": {},+    "pins": [+      {+        "number": "1",+        "name": "1OE",+        "type": "input",+        "description": "Active-low output enable for the 1Y1-1Y4 bank. When 1OE is low the 1A1-1A4 inputs are driven onto 1Y1-1Y4; when high the 1Y outputs enter the high-impedance (Hi-Z) state."+      },+      {+        "number": "2",+        "name": "1A1",+        "type": "input",+        "description": "Port 1 channel A1 data input. Accepts CMOS logic levels up to 5.5 V independent of VCC (VCC 1.65-3.6 V)."+      },+      {+        "number": "3",+        "name": "2Y4",+        "type": "tri_state",+        "description": "Port 2 channel Y4 buffered 3-state output. Follows 2A4 when 2OE is low, Hi-Z when 2OE is high. IOH/IOL up to +/-24 mA at VCC=3 V."+      },+      {+        "number": "4",+        "name": "1A2",+        "type": "input",+        "description": "Port 1 channel A2 data input. Accepts CMOS logic levels up to 5.5 V independent of VCC."+      },+      {+        "number": "5",+        "name": "2Y3",+        "type": "tri_state",+        "description": "Port 2 channel Y3 buffered 3-state output. Follows 2A3 when 2OE is low, Hi-Z when 2OE is high."+      },+      {+        "number": "6",+        "name": "1A3",+        "type": "input",+        "description": "Port 1 channel A3 data input. Accepts CMOS logic levels up to 5.5 V."+      },+      {+        "number": "7",+        "name": "2Y2",+        "type": "tri_state",+        "description": "Port 2 channel Y2 buffered 3-state output. Follows 2A2 when 2OE is low, Hi-Z when 2OE is high."+      },+      {+        "number": "8",+        "name": "1A4",+        "type": "input",+        "description": "Port 1 channel A4 data input. Accepts CMOS logic levels up to 5.5 V."+      },+      {+        "number": "9",+        "name": "2Y1",+        "type": "tri_state",+        "description": "Port 2 channel Y1 buffered 3-state output. Follows 2A1 when 2OE is low, Hi-Z when 2OE is high."+      },+      {+        "number": "10",+        "name": "GND",+        "type": "power_in",+        "description": "Ground reference (0 V)."+      },+      {+        "number": "11",+        "name": "2A1",+        "type": "input",+        "description": "Port 2 channel A1 data input. Accepts CMOS logic levels up to 5.5 V."+      },+      {+        "number": "12",+        "name": "1Y4",+        "type": "tri_state",+        "description": "Port 1 channel Y4 buffered 3-state output. Follows 1A4 when 1OE is low, Hi-Z when 1OE is high."+      },+      {+        "number": "13",+        "name": "2A2",+        "type": "input",+        "description": "Port 2 channel A2 data input. Accepts CMOS logic levels up to 5.5 V."+      },+      {+        "number": "14",+        "name": "1Y3",+        "type": "tri_state",+        "description": "Port 1 channel Y3 buffered 3-state output. Follows 1A3 when 1OE is low, Hi-Z when 1OE is high."+      },+      {+        "number": "15",+        "name": "2A3",+        "type": "input",+        "description": "Port 2 channel A3 data input. Accepts CMOS logic levels up to 5.5 V."+      },+      {+        "number": "16",+        "name": "1Y2",+        "type": "tri_state",+        "description": "Port 1 channel Y2 buffered 3-state output. Follows 1A2 when 1OE is low, Hi-Z when 1OE is high."+      },+      {+        "number": "17",+        "name": "2A4",+        "type": "input",+        "description": "Port 2 channel A4 data input. Accepts CMOS logic levels up to 5.5 V."+      },+      {+        "number": "18",+        "name": "1Y1",+        "type": "tri_state",+        "description": "Port 1 channel Y1 buffered 3-state output. Follows 1A1 when 1OE is low, Hi-Z when 1OE is high."+      },+      {+        "number": "19",+        "name": "2OE",+        "type": "input",+        "description": "Active-low output enable for the 2Y1-2Y4 bank. When 2OE is low the 2A1-2A4 inputs are driven onto 2Y1-2Y4; when high the 2Y outputs enter Hi-Z."+      },+      {+        "number": "20",+        "name": "VCC",+        "type": "power_in",+        "description": "Supply voltage. Operating range 1.65 V to 3.6 V (data retention >=1.5 V). Absolute maximum 6.5 V."+      }+    ],+    "provenance": {+      "extractor": "ds2sf",+      "datasheet": {+        "url": "https://www.ti.com/lit/ds/symlink/sn74lvc244adbr.pdf",+        "pages": 36,+        "sha256": "6fe0efecbb5e363d",+        "source_tier": "mfr"+      },+      "cad": "KiCad official (CC-BY-SA 4.0)",+      "pins": {+        "total": 20,+        "described": 20,+        "cites_pages": true,+        "refuses_to_fabricate": true+      }+    },+    "viewers": {+      "symbol": "viewers/symbol.html",+      "footprint": "viewers/footprint.html"+    }+  },+  "metadata": {+    "specs": {+      "Manufacturer": "Texas Instruments",+      "Package": "SSOP-20-208mil",+      "Category": "Logic",+      "Pins": "20"+    }+  },+  "variants": [+    {+      "mpn": "SN74LVC244ADBR",+      "kind": "packaging"+    },+    {+      "mpn": "SN74LVC244ADBRAN",+      "kind": "packaging"+    },+    {+      "mpn": "SN74LVC244ADBRANS",+      "kind": "packaging"+    },+    {+      "mpn": "SN74LVC244ADBRADGV",+      "kind": "packaging"+    },+    {+      "mpn": "SN74LVC244ADBRADW",+      "kind": "packaging"+    },+    {+      "mpn": "SN74LVC244ADBRARGY",+      "kind": "packaging"+    },+    {+      "mpn": "SN74LVC244ADBRAZQN",+      "kind": "packaging"+    },+    {+      "mpn": "SN74LVC244ADBRAPW",+      "kind": "packaging"+    },+    {+      "mpn": "SN74LVC244ADBRARWP",+      "kind": "packaging"+    }+  ],+  "sections": [+    "hero",+    "viewers",+    "readme",+    "breadcrumbs",+    "info"+  ],+  "discovery_triggers": [+    "sn74lvc244adbr"+  ],+  "discovery_pitch": "SN74LVC244ADBR (Texas Instruments) component page with datasheet-verified CAD.",+  "author": {+    "name": "Ray",+    "email": "[email protected]"+  },   "dependencies": {},   "hero": {     "type": "image",@@ -25,10 +248,5 @@     "docs/sn74lvc244adbr-datasheet.pdf",     "viewers/symbol.html",     "viewers/footprint.html"-  ],-  "visibility": "public",-  "author": {-    "name": "Ray",-    "email": "[email protected]"-  }+  ] }\ No newline at end of file