SN74LVC1G86DCKR

{
  "schema_version": 1,
  "type": "component",
  "slug": "sn74lvc1g86dckr",
  "title": "SN74LVC1G86DCKR",
  "brief": "UMW Gates, SC-70-5. Pinout extracted from the datasheet, KiCad symbol/footprint/3D.",
  "version": "0.2.0",
  "license": "CC-BY-SA-4.0",
  "tags": [
    "component",
    "logic",
    "sn74lvc1g86dckr"
  ],
  "component": {
    "mpn": "SN74LVC1G86DCKR",
    "manufacturer": "UMW",
    "package": "SC-70-5",
    "pin_count": 5,
    "category": "Logic",
    "subcategory": "Gates",
    "datasheet": "https://wmsc.lcsc.com/wmsc/upload/file/pdf/v2/lcsc/2403220745_UMW-Youtai-Semiconductor-Co---Ltd--SN74LVC1G86DCKR-UMW_C7394027.pdf",
    "parts": {
      "symbol": "sn74lvc1g86dckr.kicad_sym",
      "footprint": "sn74lvc1g86dckr.kicad_mod",
      "model_3d": "sn74lvc1g86dckr-etched.glb",
      "model_3d_plain": "sn74lvc1g86dckr.glb",
      "model_3d_step": "sn74lvc1g86dckr-etched.step",
      "model_3d_step_plain": "sn74lvc1g86dckr.step",
      "lbr": "sn74lvc1g86dckr.lbr"
    },
    "distributor_links": {
      "digikey": "4518-SN74LVC1G86DCKRTR-ND"
    },
    "pins": [
      {
        "number": "1",
        "name": "INB",
        "type": "input",
        "description": "B-input of the 2-input XOR gate. LVCMOS/TTL compatible logic input, tolerant to VIN up to 7 V independent of VCC. VIH = 0.7·VCC (VCC 2.3-5.5 V); input leakage ±1 µA max."
      },
      {
        "number": "2",
        "name": "INA",
        "type": "input",
        "description": "A-input of the 2-input XOR gate. LVCMOS/TTL compatible logic input, tolerant to VIN up to 7 V independent of VCC. VIH = 0.7·VCC (VCC 2.3-5.5 V); input leakage ±1 µA max."
      },
      {
        "number": "3",
        "name": "GND",
        "type": "power_in",
        "description": "Ground reference (0 V) for the device. Connect to system ground."
      },
      {
        "number": "4",
        "name": "Y",
        "type": "output",
        "description": "XOR output (Y = A ⊕ B). Push-pull CMOS output, sinks up to 24 mA (IOL) and sources up to 24 mA (IOH) at VCC=3 V; pullup on this pin may be tied to a rail between 0 and 7 V."
      },
      {
        "number": "5",
        "name": "VCC",
        "type": "power_in",
        "description": "Positive supply input. Recommended operating range 1.65 V to 5.5 V (absolute max 7 V). Bypass with a 0.1 µF ceramic capacitor to GND close to the pin."
      }
    ],
    "provenance": {
      "extractor": "ds2sf",
      "datasheet": {
        "url": "https://wmsc.lcsc.com/wmsc/upload/file/pdf/v2/lcsc/2403220745_UMW-Youtai-Semiconductor-Co---Ltd--SN74LVC1G86DCKR-UMW_C7394027.pdf",
        "pages": 12,
        "sha256": "c8149b8b2f74d58d",
        "source_tier": "lcsc"
      },
      "cad": "KiCad official (CC-BY-SA 4.0)",
      "pins": {
        "total": 5,
        "described": 5,
        "cites_pages": true,
        "refuses_to_fabricate": true
      }
    },
    "viewers": {
      "symbol": "viewers/symbol.html",
      "footprint": "viewers/footprint.html"
    },
    "pin1": {
      "pad": "1",
      "at": [
        -0.8375,
        -0.65
      ],
      "corner": "top-left",
      "source": "silk-marker",
      "derived_from": "SOT-353_SC-70-5@sha256:869e17094994ff78",
      "mark": "drawn"
    },
    "logic": {
      "family_id": "74LVC1G86",
      "logic_family": "74LVC",
      "function_code": "1G86",
      "function_class": "Gate",
      "function_name": "1-gate variant of Quad 2-Input XOR Gate (86)",
      "manufacturer": "Texas Instruments",
      "is_specialty": false
    },
    "models_3d": [
      {
        "file": "sn74lvc1g86dckr.step",
        "role": "plain",
        "up": "Z",
        "units": "mm",
        "origin": "footprint origin = pad-pattern centre",
        "seat": "z = 0",
        "extents_mm": [
          2.1,
          2.0,
          1.1
        ],
        "zmin_mm": 0.0,
        "centre_offset_mm": 0.0,
        "footprint_binding": "identity",
        "sha256": "2860de5b7b085919ff6e952148353f928798588d9f544dc69430545aff2ba908",
        "checked": "2026-10-07",
        "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"
      },
      {
        "file": "sn74lvc1g86dckr-etched.step",
        "role": "eda",
        "up": "Z",
        "units": "mm",
        "origin": "footprint origin = pad-pattern centre",
        "seat": "z = 0",
        "extents_mm": [
          2.1,
          2.0,
          1.1
        ],
        "zmin_mm": 0.0,
        "centre_offset_mm": 0.0,
        "footprint_binding": "identity",
        "sha256": "1d5e26fc818d71690b9a2a4030197a4e32fbcb16ca7dcfb7c52a9c24a81031bd",
        "checked": "2026-10-07",
        "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"
      }
    ]
  },
  "metadata": {
    "specs": {
      "Manufacturer": "Unknown",
      "Package": "SC-70-5",
      "Category": "Logic",
      "Pins": "5"
    }
  },
  "sections": [
    "hero",
    "viewers",
    "readme",
    "breadcrumbs",
    "info"
  ],
  "discovery_triggers": [
    "sn74lvc1g86dckr"
  ],
  "discovery_pitch": "SN74LVC1G86DCKR (Unknown) component page with datasheet-verified CAD.",
  "author": {
    "name": "Ray",
    "email": "[email protected]"
  },
  "dependencies": {},
  "hero": {
    "type": "image",
    "path": "docs/hero.png"
  },
  "files": [
    "page.json",
    "README.md",
    "sn74lvc1g86dckr.kicad_sym",
    "sn74lvc1g86dckr.kicad_mod",
    "sn74lvc1g86dckr.glb",
    "sn74lvc1g86dckr.step",
    "sn74lvc1g86dckr-etched.step",
    "sn74lvc1g86dckr.lbr",
    "docs/hero.png",
    "docs/sn74lvc1g86dckr-datasheet.pdf",
    "viewers/symbol.html",
    "viewers/footprint.html"
  ],
  "variants": [
    {
      "mpn": "SN74LVC1G86DCKR",
      "kind": "packaging"
    },
    {
      "mpn": "SN74LVC1G86DCKRDBVR",
      "kind": "packaging"
    },
    {
      "mpn": "SN74LVC1G86DCKRDBV",
      "kind": "packaging"
    }
  ],
  "updated_at": "2026-09-25T07:39:24.539Z"
}