SN74LVC1G86DCKR

{
 "schema": "adom.pads/1",
 "slug": "sn74lvc1g86dckr",
 "footprint": "SOT-353_SC-70-5",
 "generated_from": {
  "footprint": "SOT-353_SC-70-5@sha256:869e17094994ff78",
  "pins": "page.json:component.pins",
  "overrides": null
 },
 "pin1": {
  "pad": "1",
  "at": [
   -0.8375,
   -0.65
  ],
  "corner": "top-left",
  "source": "silk-marker",
  "derived_from": "SOT-353_SC-70-5@sha256:869e17094994ff78"
 },
 "pad_count": 5,
 "symbol_pins": [
  "1",
  "2",
  "3",
  "4",
  "5"
 ],
 "paste_apertures": 0,
 "issues": [],
 "pads": [
  {
   "pad": "1",
   "kind": "smd",
   "shape": "roundrect",
   "at": [
    -0.8375,
    -0.65
   ],
   "rot": 0.0,
   "size": [
    1.025,
    0.35
   ],
   "layers": [
    "F.Cu",
    "F.Mask",
    "F.Paste"
   ],
   "thermal": false,
   "pin": "1",
   "name": "INB",
   "type": "input",
   "description": "B-input of the 2-input XOR gate. LVCMOS/TTL compatible logic input, tolerant to VIN up to 7 V independent of VCC. VIH = 0.7·VCC (VCC 2.3-5.5 V); input leakage ±1 µA max.",
   "is_pin1": true,
   "source": {
    "geometry": "SOT-353_SC-70-5.kicad_mod",
    "meaning": "page.json:component.pins",
    "correspondence": "kicad: symbol pin number == pad name"
   }
  },
  {
   "pad": "2",
   "kind": "smd",
   "shape": "roundrect",
   "at": [
    -0.8375,
    0.0
   ],
   "rot": 0.0,
   "size": [
    1.025,
    0.35
   ],
   "layers": [
    "F.Cu",
    "F.Mask",
    "F.Paste"
   ],
   "thermal": false,
   "pin": "2",
   "name": "INA",
   "type": "input",
   "description": "A-input of the 2-input XOR gate. LVCMOS/TTL compatible logic input, tolerant to VIN up to 7 V independent of VCC. VIH = 0.7·VCC (VCC 2.3-5.5 V); input leakage ±1 µA max.",
   "is_pin1": false,
   "source": {
    "geometry": "SOT-353_SC-70-5.kicad_mod",
    "meaning": "page.json:component.pins",
    "correspondence": "kicad: symbol pin number == pad name"
   }
  },
  {
   "pad": "3",
   "kind": "smd",
   "shape": "roundrect",
   "at": [
    -0.8375,
    0.65
   ],
   "rot": 0.0,
   "size": [
    1.025,
    0.35
   ],
   "layers": [
    "F.Cu",
    "F.Mask",
    "F.Paste"
   ],
   "thermal": false,
   "pin": "3",
   "name": "GND",
   "type": "power_in",
   "description": "Ground reference (0 V) for the device. Connect to system ground.",
   "is_pin1": false,
   "source": {
    "geometry": "SOT-353_SC-70-5.kicad_mod",
    "meaning": "page.json:component.pins",
    "correspondence": "kicad: symbol pin number == pad name"
   }
  },
  {
   "pad": "4",
   "kind": "smd",
   "shape": "roundrect",
   "at": [
    0.8375,
    0.65
   ],
   "rot": 0.0,
   "size": [
    1.025,
    0.35
   ],
   "layers": [
    "F.Cu",
    "F.Mask",
    "F.Paste"
   ],
   "thermal": false,
   "pin": "4",
   "name": "Y",
   "type": "output",
   "description": "XOR output (Y = A ⊕ B). Push-pull CMOS output, sinks up to 24 mA (IOL) and sources up to 24 mA (IOH) at VCC=3 V; pullup on this pin may be tied to a rail between 0 and 7 V.",
   "is_pin1": false,
   "source": {
    "geometry": "SOT-353_SC-70-5.kicad_mod",
    "meaning": "page.json:component.pins",
    "correspondence": "kicad: symbol pin number == pad name"
   }
  },
  {
   "pad": "5",
   "kind": "smd",
   "shape": "roundrect",
   "at": [
    0.8375,
    -0.65
   ],
   "rot": 0.0,
   "size": [
    1.025,
    0.35
   ],
   "layers": [
    "F.Cu",
    "F.Mask",
    "F.Paste"
   ],
   "thermal": false,
   "pin": "5",
   "name": "VCC",
   "type": "power_in",
   "description": "Positive supply input. Recommended operating range 1.65 V to 5.5 V (absolute max 7 V). Bypass with a 0.1 µF ceramic capacitor to GND close to the pin.",
   "is_pin1": false,
   "source": {
    "geometry": "SOT-353_SC-70-5.kicad_mod",
    "meaning": "page.json:component.pins",
    "correspondence": "kicad: symbol pin number == pad name"
   }
  }
 ]
}