component
SN74LVC1G86DCKR
Public Made by Adomby adom
UMW Gates, SC-70-5. Pinout extracted from the datasheet, KiCad symbol/footprint/3D.
← Commit history
sn74lvc1g86dckr: manufacturer provenance fix
2 files changed
+122−125
README.md+4−4@@ -1,8 +1,8 @@ # SN74LVC1G86DCKR -**Unknown** · Gates · SC-70-5+**UMW** · Gates · SC-70-5 -SN74LVC1G86DCKR from Unknown, in a SC-70-5. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.+SN74LVC1G86DCKR from UMW, in a SC-70-5. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD. ## Pinout @@ -18,7 +18,7 @@ SN74LVC1G86DCKR from Unknown, in a SC-70-5. Pinout and pin descriptions extracte | Parameter | Value | |---|---|-| Manufacturer | Unknown |+| Manufacturer | UMW | | Package | SC-70-5 | | Category | Logic | | Pins | 5 |@@ -40,7 +40,7 @@ SN74LVC1G86DCKR from Unknown, in a SC-70-5. Pinout and pin descriptions extracte Data extracted from the manufacturer datasheet, not a distributor listing: -- **Datasheet:** [Unknown datasheet](docs/sn74lvc1g86dckr-datasheet.pdf) (12 pp, sha256 `c8149b8b2f74d58d`, retrieved 2026-08-17, tier: lcsc)+- **Datasheet:** [UMW datasheet](docs/sn74lvc1g86dckr-datasheet.pdf) (12 pp, sha256 `c8149b8b2f74d58d`, retrieved 2026-08-17, tier: lcsc) - **Extractor:** `ds2sf` (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate. - **CAD:** KiCad official libraries (CC-BY-SA 4.0).
page.json+118−121@@ -1,127 +1,124 @@ {- "schema_version": 1,- "type": "component",- "slug": "sn74lvc1g86dckr",- "title": "SN74LVC1G86DCKR",- "brief": "Unknown Gates, SC-70-5. Datasheet-verified pinout, KiCad symbol/footprint/3D.",- "version": "0.1.0",- "license": "CC-BY-SA-4.0",- "tags": [- "component",- "logic",- "sn74lvc1g86dckr"- ],- "component": {- "mpn": "SN74LVC1G86DCKR",- "manufacturer": "Unknown",- "package": "SC-70-5",- "pin_count": 5,- "category": "Logic",- "subcategory": "Gates",- "datasheet": "https://wmsc.lcsc.com/wmsc/upload/file/pdf/v2/lcsc/2403220745_UMW-Youtai-Semiconductor-Co---Ltd--SN74LVC1G86DCKR-UMW_C7394027.pdf",- "parts": {- "symbol": "sn74lvc1g86dckr.kicad_sym",- "footprint": "sn74lvc1g86dckr.kicad_mod",- "model_3d": "sn74lvc1g86dckr.glb",- "model_3d_step": "sn74lvc1g86dckr.step",- "lbr": "sn74lvc1g86dckr.lbr"- },- "distributor_links": {},- "pins": [- {- "number": "1",- "name": "INB",- "type": "input",- "description": "B-input of the 2-input XOR gate. LVCMOS/TTL compatible logic input, tolerant to VIN up to 7 V independent of VCC. VIH = 0.7·VCC (VCC 2.3-5.5 V); input leakage ±1 µA max."- },- {- "number": "2",- "name": "INA",- "type": "input",- "description": "A-input of the 2-input XOR gate. LVCMOS/TTL compatible logic input, tolerant to VIN up to 7 V independent of VCC. VIH = 0.7·VCC (VCC 2.3-5.5 V); input leakage ±1 µA max."- },- {- "number": "3",- "name": "GND",- "type": "power_in",- "description": "Ground reference (0 V) for the device. Connect to system ground."- },- {- "number": "4",- "name": "Y",- "type": "output",- "description": "XOR output (Y = A ⊕ B). Push-pull CMOS output, sinks up to 24 mA (IOL) and sources up to 24 mA (IOH) at VCC=3 V; pullup on this pin may be tied to a rail between 0 and 7 V."- },- {- "number": "5",- "name": "VCC",- "type": "power_in",- "description": "Positive supply input. Recommended operating range 1.65 V to 5.5 V (absolute max 7 V). Bypass with a 0.1 µF ceramic capacitor to GND close to the pin."- }- ],- "provenance": {- "extractor": "ds2sf",- "datasheet": {- "url": "https://wmsc.lcsc.com/wmsc/upload/file/pdf/v2/lcsc/2403220745_UMW-Youtai-Semiconductor-Co---Ltd--SN74LVC1G86DCKR-UMW_C7394027.pdf",- "pages": 12,- "sha256": "c8149b8b2f74d58d",- "source_tier": "lcsc"- },- "cad": "KiCad official (CC-BY-SA 4.0)",- "pins": {- "total": 5,- "described": 5,- "cites_pages": true,- "refuses_to_fabricate": true- }- },- "viewers": {- "symbol": "viewers/symbol.html",- "footprint": "viewers/footprint.html"- }- },- "metadata": {- "specs": {- "Manufacturer": "Unknown",- "Package": "SC-70-5",- "Category": "Logic",- "Pins": "5"- }+ "schema_version": 1,+ "type": "component",+ "slug": "sn74lvc1g86dckr",+ "title": "SN74LVC1G86DCKR",+ "brief": "UMW Gates, SC-70-5. Datasheet-verified pinout, KiCad symbol/footprint/3D.",+ "version": "0.1.0",+ "license": "CC-BY-SA-4.0",+ "tags": [+ "component",+ "logic",+ "sn74lvc1g86dckr"+ ],+ "component": {+ "mpn": "SN74LVC1G86DCKR",+ "manufacturer": "UMW",+ "package": "SC-70-5",+ "pin_count": 5,+ "category": "Logic",+ "subcategory": "Gates",+ "datasheet": "https://wmsc.lcsc.com/wmsc/upload/file/pdf/v2/lcsc/2403220745_UMW-Youtai-Semiconductor-Co---Ltd--SN74LVC1G86DCKR-UMW_C7394027.pdf",+ "parts": {+ "symbol": "sn74lvc1g86dckr.kicad_sym",+ "footprint": "sn74lvc1g86dckr.kicad_mod",+ "model_3d": "sn74lvc1g86dckr.glb",+ "model_3d_step": "sn74lvc1g86dckr.step",+ "lbr": "sn74lvc1g86dckr.lbr" },- "sections": [- "hero",- "viewers",- "readme",- "breadcrumbs",- "info"- ],- "discovery_triggers": [- "sn74lvc1g86dckr"+ "distributor_links": {},+ "pins": [+ {+ "number": "1",+ "name": "INB",+ "type": "input",+ "description": "B-input of the 2-input XOR gate. LVCMOS/TTL compatible logic input, tolerant to VIN up to 7 V independent of VCC. VIH = 0.7\u00b7VCC (VCC 2.3-5.5 V); input leakage \u00b11 \u00b5A max."+ },+ {+ "number": "2",+ "name": "INA",+ "type": "input",+ "description": "A-input of the 2-input XOR gate. LVCMOS/TTL compatible logic input, tolerant to VIN up to 7 V independent of VCC. VIH = 0.7\u00b7VCC (VCC 2.3-5.5 V); input leakage \u00b11 \u00b5A max."+ },+ {+ "number": "3",+ "name": "GND",+ "type": "power_in",+ "description": "Ground reference (0 V) for the device. Connect to system ground."+ },+ {+ "number": "4",+ "name": "Y",+ "type": "output",+ "description": "XOR output (Y = A \u2295 B). Push-pull CMOS output, sinks up to 24 mA (IOL) and sources up to 24 mA (IOH) at VCC=3 V; pullup on this pin may be tied to a rail between 0 and 7 V."+ },+ {+ "number": "5",+ "name": "VCC",+ "type": "power_in",+ "description": "Positive supply input. Recommended operating range 1.65 V to 5.5 V (absolute max 7 V). Bypass with a 0.1 \u00b5F ceramic capacitor to GND close to the pin."+ } ],- "discovery_pitch": "SN74LVC1G86DCKR (Unknown) component page with datasheet-verified CAD.",- "author": {- "name": "Ray",- "email": "[email protected]"+ "provenance": {+ "extractor": "ds2sf",+ "datasheet": {+ "url": "https://wmsc.lcsc.com/wmsc/upload/file/pdf/v2/lcsc/2403220745_UMW-Youtai-Semiconductor-Co---Ltd--SN74LVC1G86DCKR-UMW_C7394027.pdf",+ "pages": 12,+ "sha256": "c8149b8b2f74d58d",+ "source_tier": "lcsc"+ },+ "cad": "KiCad official (CC-BY-SA 4.0)",+ "pins": {+ "total": 5,+ "described": 5,+ "cites_pages": true,+ "refuses_to_fabricate": true+ } },- "dependencies": {},- "hero": {- "type": "image",- "path": "docs/hero.png"- },- "files": [- "page.json",- "README.md",- "sn74lvc1g86dckr.kicad_sym",- "sn74lvc1g86dckr.kicad_mod",- "sn74lvc1g86dckr.glb",- "sn74lvc1g86dckr.step",- "sn74lvc1g86dckr.lbr",- "docs/hero.png",- "docs/sn74lvc1g86dckr-datasheet.pdf",- "viewers/symbol.html",- "viewers/footprint.html"- ],- "visibility": {- "public": true+ "viewers": {+ "symbol": "viewers/symbol.html",+ "footprint": "viewers/footprint.html"+ }+ },+ "metadata": {+ "specs": {+ "Manufacturer": "Unknown",+ "Package": "SC-70-5",+ "Category": "Logic",+ "Pins": "5" }+ },+ "sections": [+ "hero",+ "viewers",+ "readme",+ "breadcrumbs",+ "info"+ ],+ "discovery_triggers": [+ "sn74lvc1g86dckr"+ ],+ "discovery_pitch": "SN74LVC1G86DCKR (Unknown) component page with datasheet-verified CAD.",+ "author": {+ "name": "Ray",+ "email": "[email protected]"+ },+ "dependencies": {},+ "hero": {+ "type": "image",+ "path": "docs/hero.png"+ },+ "files": [+ "page.json",+ "README.md",+ "sn74lvc1g86dckr.kicad_sym",+ "sn74lvc1g86dckr.kicad_mod",+ "sn74lvc1g86dckr.glb",+ "sn74lvc1g86dckr.step",+ "sn74lvc1g86dckr.lbr",+ "docs/hero.png",+ "docs/sn74lvc1g86dckr-datasheet.pdf",+ "viewers/symbol.html",+ "viewers/footprint.html"+ ] }