component
SN74LVC1G374DBVR
Public Made by Adomby adom
Texas Instruments Flip Flops, SOT-23-6. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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README.mdadded+42@@ -0,0 +1,42 @@+# SN74LVC1G374DBVR++**Texas Instruments** · Flip Flops · SOT-23-6++SN74LVC1G374DBVR from Texas Instruments, in a SOT-23-6. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.++## Pinout++| Pin | Name | Type | Function |+|---|---|---|---|+| 1 | CLK | input | Clock input; Q captures D on positive edge when OE is low; maximum clock frequency 175 MHz at 5 V. |+| 2 | GND | power_in | Ground, 0 V reference. |+| 3 | D | input | Data input; value is latched at Q on positive CLK edge when OE is low; minimum setup time 1.5 ns before CLK ↑ at 5 V. |+| 4 | Q | tri_state | 3-state output; driven high or low by latched D when OE = low (propagation delay 1-4 ns at 5 V with 15 pF load), high-impedance when OE = high. |+| 5 | VCC | power_in | Positive supply voltage; 1.65 V to 5.5 V range for normal operation and 5 V logic input compatibility. |+| 6 | OE | input | Output Enable (active low); OE = low enables Q output, OE = high forces Q to high-impedance; transition time 1.1-3.1 ns at 5 V. |++## Key specifications++| Parameter | Value |+|---|---|+| Manufacturer | Texas Instruments |+| Package | SOT-23-6 |+| Category | Logic |+| Pins | 6 |++## CAD (KiCad official)++- Symbol: `SN74LVC1G374DBVR`+- Footprint: `Package_TO_SOT_SMD:SOT-23-6`+- 3D model: SOT-23-6 (KiCad packages3D, STEP)+- 3D model files: `sn74lvc1g374dbvr-etched.step` / `sn74lvc1g374dbvr-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `sn74lvc1g374dbvr.step` / `sn74lvc1g374dbvr.glb` are the bare package body.++## Provenance++Data extracted from the manufacturer datasheet, not a distributor listing:++- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/lit/ds/symlink/sn74lvc1g374.pdf) (22 pp, sha256 `f641a061071feb1e`, retrieved 2026-09-23, tier: manufacturer)+- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.2`, primary `claude-haiku-4-5-20251001` (text), consensus `claude-sonnet-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.+- **CAD:** KiCad official libraries (CC-BY-SA 4.0).++[Datasheet PDF](docs/sn74lvc1g374dbvr-datasheet.pdf)
page.jsonadded+129@@ -0,0 +1,129 @@+{+ "slug": "sn74lvc1g374dbvr",+ "version": "0.1.0",+ "type": "component",+ "description": "Texas Instruments Flip Flops, SOT-23-6. Datasheet-verified pinout, KiCad symbol/footprint/3D.",+ "tags": [+ "component",+ "logic",+ "sn74lvc1g374dbvr",+ "factory-2.0.0",+ "extractor-text"+ ],+ "dependencies": {},+ "hero": {+ "type": "image",+ "path": "docs/hero.png"+ },+ "files": [+ "page.json",+ "README.md",+ "sn74lvc1g374dbvr.kicad_sym",+ "sn74lvc1g374dbvr.kicad_mod",+ "sn74lvc1g374dbvr.glb",+ "sn74lvc1g374dbvr.step",+ "sn74lvc1g374dbvr.lbr",+ "docs/hero.png",+ "docs/sn74lvc1g374dbvr-datasheet.pdf",+ "viewers/symbol.html",+ "viewers/footprint.html"+ ],+ "component": {+ "mpn": "SN74LVC1G374DBVR",+ "manufacturer": "Texas Instruments",+ "package": "SOT-23-6",+ "pin_count": 6,+ "category": "Logic",+ "subcategory": "Flip Flops",+ "datasheet": "https://www.ti.com/lit/ds/symlink/sn74lvc1g374.pdf",+ "parts": {+ "symbol": "sn74lvc1g374dbvr.kicad_sym",+ "footprint": "sn74lvc1g374dbvr.kicad_mod",+ "model_3d": "sn74lvc1g374dbvr-etched.glb",+ "model_3d_plain": "sn74lvc1g374dbvr.glb",+ "model_3d_step": "sn74lvc1g374dbvr-etched.step",+ "model_3d_step_plain": "sn74lvc1g374dbvr.step",+ "lbr": "sn74lvc1g374dbvr.lbr"+ },+ "distributor_links": {+ "lcsc": "C76555"+ },+ "pins": [+ {+ "number": "1",+ "name": "CLK",+ "type": "input",+ "description": "Clock input; Q captures D on positive edge when OE is low; maximum clock frequency 175 MHz at 5 V."+ },+ {+ "number": "2",+ "name": "GND",+ "type": "power_in",+ "description": "Ground, 0 V reference."+ },+ {+ "number": "3",+ "name": "D",+ "type": "input",+ "description": "Data input; value is latched at Q on positive CLK edge when OE is low; minimum setup time 1.5 ns before CLK ↑ at 5 V."+ },+ {+ "number": "4",+ "name": "Q",+ "type": "tri_state",+ "description": "3-state output; driven high or low by latched D when OE = low (propagation delay 1-4 ns at 5 V with 15 pF load), high-impedance when OE = high."+ },+ {+ "number": "5",+ "name": "VCC",+ "type": "power_in",+ "description": "Positive supply voltage; 1.65 V to 5.5 V range for normal operation and 5 V logic input compatibility."+ },+ {+ "number": "6",+ "name": "OE",+ "type": "input",+ "description": "Output Enable (active low); OE = low enables Q output, OE = high forces Q to high-impedance; transition time 1.1-3.1 ns at 5 V."+ }+ ],+ "provenance": {+ "extractor": "extract_pins 0.2",+ "factory_chain": {+ "factory": "2.0.0",+ "extractor": "extract_pins 0.2",+ "primary_model": "claude-haiku-4-5-20251001",+ "primary_mode": "text",+ "consensus_model": "claude-sonnet-5",+ "consensus": "agreed",+ "guards": "pin_guards 0.1: passed",+ "guard_notes": [],+ "pages_sent": 22,+ "cost_usd": 0.2364,+ "at": "2026-09-23T19:47:05"+ },+ "datasheet": {+ "url": "https://www.ti.com/lit/ds/symlink/sn74lvc1g374.pdf",+ "pages": 22,+ "sha256": "f641a061071feb1e",+ "source_tier": "mfr"+ },+ "cad": "KiCad official (CC-BY-SA 4.0)",+ "pins": {+ "total": 6,+ "described": 6,+ "cites_pages": true,+ "refuses_to_fabricate": true+ }+ },+ "viewers": {+ "symbol": "viewers/symbol.html",+ "footprint": "viewers/footprint.html"+ }+ },+ "visibility": "public",+ "org": "adom",+ "author": {+ "name": "Ray",+ "email": "[email protected]"+ }+}