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Contents

README

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SN74LVC1G374DBVR

Texas Instruments · Flip Flops · SOT-23-6

SN74LVC1G374DBVR from Texas Instruments, in a SOT-23-6. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 CLK input Clock input; Q captures D on positive edge when OE is low; maximum clock frequency 175 MHz at 5 V.
2 GND power_in Ground, 0 V reference.
3 D input Data input; value is latched at Q on positive CLK edge when OE is low; minimum setup time 1.5 ns before CLK ↑ at 5 V.
4 Q tri_state 3-state output; driven high or low by latched D when OE = low (propagation delay 1-4 ns at 5 V with 15 pF load), high-impedance when OE = high.
5 VCC power_in Positive supply voltage; 1.65 V to 5.5 V range for normal operation and 5 V logic input compatibility.
6 OE input Output Enable (active low); OE = low enables Q output, OE = high forces Q to high-impedance; transition time 1.1-3.1 ns at 5 V.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package SOT-23-6
Category Logic
Pins 6

CAD (KiCad official)

  • Symbol: SN74LVC1G374DBVR
  • Footprint: Package_TO_SOT_SMD:SOT-23-6
  • 3D model: SOT-23-6 (KiCad packages3D, STEP)
  • 3D model files: sn74lvc1g374dbvr-etched.step / sn74lvc1g374dbvr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); sn74lvc1g374dbvr.step / sn74lvc1g374dbvr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (22 pp, sha256 f641a061071feb1e, retrieved 2026-09-23, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.2, primary claude-haiku-4-5-20251001 (text), consensus claude-sonnet-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF