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Contents

README

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SN74LVC1G32IDCKREP

Texas Instruments · Gates · SC-70-5

SN74LVC1G32IDCKREP from Texas Instruments, in a SC-70-5. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 A input Logic input A of the 2-input OR gate, accepts voltages up to 5.5 V and must be held at VCC or GND when unused.
2 B input Logic input B of the 2-input OR gate, accepts voltages up to 5.5 V and must be held at VCC or GND when unused.
3 GND power_in Ground reference for the device.
4 Y output Gate output Y = A + B in positive logic, drives up to ±24 mA at 3.3 V and is disabled by Ioff when the device is powered down.
5 VCC power_in Supply voltage, 1.65 V to 5.5 V operating range.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package SC-70-5
Category Logic ICs
Pins 5

CAD (KiCad official)

  • Symbol: SN74LVC1G32IDCKREP
  • Footprint: Package_TO_SOT_SMD:SOT-353_SC-70-5
  • 3D model: SC-70-5 (KiCad packages3D, STEP)
  • 3D model files: sn74lvc1g32idckrep-etched.step / sn74lvc1g32idckrep-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); sn74lvc1g32idckrep.step / sn74lvc1g32idckrep.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (16 pp, sha256 61b52a8c39175a45, retrieved 2026-10-28, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text+vision), consensus claude-opus-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF