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Contents

README

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SN74LVC1G32DRLR

Texas Instruments · Logic Gates · SOT-553-5

SN74LVC1G32DRLR from Texas Instruments, in a SOT-553-5. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 A input Input A to the 2-input OR gate; input voltage range -0.5V to 6.5V absolute maximum; supports down-translation.
2 B input Input B to the 2-input OR gate; input voltage range -0.5V to 6.5V absolute maximum; supports down-translation.
3 GND power_in Ground reference pin; continuous current capability ±100mA.
4 Y output Output Y of the positive-logic OR gate; provides ±24mA output drive at 3.3V supply voltage.
5 VCC power_in Power supply pin; VCC range -0.5V to 6.5V absolute maximum; continuous current ±100mA.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package SOT-553-5
Category Logic
Pins 5

CAD (KiCad official)

  • Symbol: SN74LVC1G32DRLR
  • Footprint: Package_TO_SOT_SMD:SOT-553
  • 3D model: SOT-553-5 (KiCad packages3D, STEP)
  • 3D model files: sn74lvc1g32drlr-etched.step / sn74lvc1g32drlr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); sn74lvc1g32drlr.step / sn74lvc1g32drlr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (51 pp, sha256 b64786a568abe6a7, retrieved 2026-10-01, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-4-5-20251001 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF