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docs sn74lvc1g32dckr: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray
viewers pin 1: carry the footprint's marker into the .lbr, the viewer and page.json (silk-marker, drawn, top-left) · Ray
package.json Publish 0.2.0 · Ray
pads.json pin 1: carry the footprint's marker into the .lbr, the viewer and page.json (silk-marker, drawn, top-left) · Ray
page.json sn74lvc1g32dckr: white body in tscircuit (pre-1.8 etch structure under an assembly instance); Ray 2026-10-19: black IC… · Ray
README.md sn74lvc1g32dckr: laser-etched CAD + chip hero (factory 2.0.0 backfill) · Ray
sn74lvc1g32dckr-etched.fit.json sn74lvc1g32dckr: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray
sn74lvc1g32dckr-etched.glb sn74lvc1g32dckr: white body in tscircuit (pre-1.8 etch structure under an assembly instance); Ray 2026-10-19: black IC… · Ray
sn74lvc1g32dckr-etched.step sn74lvc1g32dckr: white body in tscircuit (pre-1.8 etch structure under an assembly instance); Ray 2026-10-19: black IC… · Ray
sn74lvc1g32dckr.glb Publish 0.1.0 · Ray
sn74lvc1g32dckr.kicad_mod Publish 0.1.0 · Ray
sn74lvc1g32dckr.kicad_sym Publish 0.1.0 · Ray
sn74lvc1g32dckr.lbr rebuild the library on adom-lbr 2.32.0. The published copy was built by 2.18.0, which imported every KiCad roundrect an… · Ray
sn74lvc1g32dckr.step Publish 0.1.0 · Ray

SN74LVC1G32DCKR

Texas Instruments · Gates · SC-70-5

SN74LVC1G32DCKR from Texas Instruments, in a SC-70-5. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 A input Logic input A of the 2-input OR gate. Accepts CMOS logic levels up to 5.5 V regardless of VCC (enables voltage down-translation).
2 B input Logic input B of the 2-input OR gate. Accepts CMOS logic levels up to 5.5 V regardless of VCC.
3 GND power_in Device ground reference (0 V). Must be connected to system ground.
4 Y output OR-gate output, Y = A + B. Push-pull CMOS output rated ±24 mA drive at VCC = 3.3 V.
5 VCC power_in Positive supply pin. Recommended operating range 1.65 V to 5.5 V (Absolute Max 6.5 V). Bypass with a 0.1 µF ceramic capacitor to GND close to the pin.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package SC-70-5
Category Logic
Pins 5

Ordering variants

Same part, different packaging or reel option.

  • SN74LVC1G32DCKR
  • SN74LVC1G32DCKRDCKT
  • SN74LVC1G32DCKRDBV
  • SN74LVC1G32DCKRDBVR
  • SN74LVC1G32DCKRDBVT
  • SN74LVC1G32DCKRDRL
  • SN74LVC1G32DCKRDRLR
  • SN74LVC1G32DCKRDPW
  • SN74LVC1G32DCKRDPWR
  • SN74LVC1G32DCKRYZP
  • SN74LVC1G32DCKRYZPR
  • SN74LVC1G32DCKRDRY
  • SN74LVC1G32DCKRDRYR
  • SN74LVC1G32DCKRDSF
  • SN74LVC1G32DCKRDSFR

CAD (KiCad official)

  • Symbol: SN74LVC1G32DCKR
  • Footprint: Package_TO_SOT_SMD:SOT-353_SC-70-5
  • 3D model: SC-70-5 (KiCad packages3D, STEP)
  • 3D model files: sn74lvc1g32dckr-etched.step / sn74lvc1g32dckr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); sn74lvc1g32dckr.step / sn74lvc1g32dckr.glb are the bare package body.

3D model downloads

Two STEP files. Same geometry, different body top:

File Size Use it when
sn74lvc1g32dckr.step 87 KB You want the bare part, or you mark your own boards.
sn74lvc1g32dckr-etched.step 2.5 MB You want the part with SN74LVC1G32DCKR already on it.

The marking in the etched file is real recessed geometry cut into the solid, not a texture or a decal: 620 faces against 102 in the bare model. It survives export, section views, and rendering in any CAD tool, and it drops straight into KiCad or Fusion with no extra setup.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (51 pp, sha256 b64786a568abe6a7, retrieved 2026-08-17, tier: manufacturer)
  • Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF