component
SN74LVC1G32DCK3
Public Made by Adomby adom
Texas Instruments Logic Gates, SC-70-5. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
← Commit history
README.mdadded+42@@ -0,0 +1,42 @@+# SN74LVC1G32DCK3++**Texas Instruments** · Logic Gates · SC-70-5++SN74LVC1G32DCK3 from Texas Instruments, in a SC-70-5. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.++## Pinout++| Pin | Name | Type | Function |+|---|---|---|---|+| 1 | A | input | Logic input A of the 2-input OR gate (Y = A + B); unused inputs must be tied to VCC or GND, and the datasheet gives a 0 to 5.5 V input voltage range. |+| 2 | B | input | Logic input B of the 2-input OR gate (Y = A + B); unused inputs must be tied to VCC or GND, and the datasheet gives a 0 to 5.5 V input voltage range. |+| 3 | GND | power_in | Ground pin; it must be able to sink the total output current plus the maximum supply current ICC and any switching transient current. |+| 4 | Y | output | OR gate output from a balanced CMOS push-pull stage, rated at ±24 mA at 3.3 V; unused outputs may be left open but must not be connected directly to VCC or GND. |+| 5 | VCC | power_in | Supply pin with a recommended operating range of 1.65 V to 5.5 V; a decoupling capacitor should be placed close to this pin and GND. |++## Key specifications++| Parameter | Value |+|---|---|+| Manufacturer | Texas Instruments |+| Package | SC-70-5 |+| Category | Logic |+| Pins | 5 |++## CAD (KiCad official)++- Symbol: `SN74LVC1G32DCK3`+- Footprint: `Package_TO_SOT_SMD:SOT-353_SC-70-5`+- 3D model: SC-70-5 (KiCad packages3D, STEP)+- 3D model files: `sn74lvc1g32dck3-etched.step` / `sn74lvc1g32dck3-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `sn74lvc1g32dck3.step` / `sn74lvc1g32dck3.glb` are the bare package body.++## Provenance++Data extracted from the manufacturer datasheet, not a distributor listing:++- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/cn/lit/gpn/sn74lvc1g32) (51 pp, sha256 `4328a2a798937dad`, retrieved 2026-10-08, tier: lcsc)+- **Datasheet language:** Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.+- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.+- **CAD:** KiCad official libraries (CC-BY-SA 4.0).++[Datasheet PDF](docs/sn74lvc1g32dck3-datasheet.pdf)
page.jsonadded+183@@ -0,0 +1,183 @@+{+ "slug": "sn74lvc1g32dck3",+ "version": "0.1.0",+ "type": "component",+ "description": "Texas Instruments Logic Gates, SC-70-5. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.",+ "tags": [+ "component",+ "logic",+ "sn74lvc1g32dck3",+ "factory-2.0.0",+ "extractor-text"+ ],+ "dependencies": {},+ "hero": {+ "type": "image",+ "path": "docs/hero.png"+ },+ "files": [+ "page.json",+ "README.md",+ "sn74lvc1g32dck3.kicad_sym",+ "sn74lvc1g32dck3.kicad_mod",+ "sn74lvc1g32dck3.glb",+ "sn74lvc1g32dck3.step",+ "sn74lvc1g32dck3.lbr",+ "docs/hero.png",+ "docs/sn74lvc1g32dck3-datasheet.pdf",+ "viewers/symbol.html",+ "viewers/footprint.html",+ "sn74lvc1g32dck3-hero.glb",+ "sn74lvc1g32dck3-hero.overlay.json"+ ],+ "component": {+ "mpn": "SN74LVC1G32DCK3",+ "manufacturer": "Texas Instruments",+ "package": "SC-70-5",+ "pin_count": 5,+ "category": "Logic",+ "subcategory": "Logic Gates",+ "datasheet": "https://www.ti.com/cn/lit/gpn/sn74lvc1g32",+ "parts": {+ "symbol": "sn74lvc1g32dck3.kicad_sym",+ "footprint": "sn74lvc1g32dck3.kicad_mod",+ "model_3d": "sn74lvc1g32dck3-hero.glb",+ "model_3d_plain": "sn74lvc1g32dck3.glb",+ "model_3d_step": "sn74lvc1g32dck3-etched.step",+ "model_3d_step_plain": "sn74lvc1g32dck3.step",+ "lbr": "sn74lvc1g32dck3.lbr"+ },+ "distributor_links": {+ "lcsc": "C2878906",+ "digikey": "296-SN74LVC1G32DCK3TR-ND",+ "mouser": "595-SN74LVC1G32DCK3"+ },+ "distributor_check": {+ "checked_at": "2026-10-08T20:23:20Z",+ "source": "Component Ocean /api/assign-pns",+ "digikey": {+ "pn": "296-SN74LVC1G32DCK3TR-ND",+ "status": "found",+ "lifecycle": "Obsolete"+ },+ "mouser": {+ "pn": "595-SN74LVC1G32DCK3",+ "status": "found",+ "lifecycle": "Obsolete"+ }+ },+ "pins": [+ {+ "number": "1",+ "name": "A",+ "type": "input",+ "description": "Logic input A of the 2-input OR gate (Y = A + B); unused inputs must be tied to VCC or GND, and the datasheet gives a 0 to 5.5 V input voltage range."+ },+ {+ "number": "2",+ "name": "B",+ "type": "input",+ "description": "Logic input B of the 2-input OR gate (Y = A + B); unused inputs must be tied to VCC or GND, and the datasheet gives a 0 to 5.5 V input voltage range."+ },+ {+ "number": "3",+ "name": "GND",+ "type": "power_in",+ "description": "Ground pin; it must be able to sink the total output current plus the maximum supply current ICC and any switching transient current."+ },+ {+ "number": "4",+ "name": "Y",+ "type": "output",+ "description": "OR gate output from a balanced CMOS push-pull stage, rated at ±24 mA at 3.3 V; unused outputs may be left open but must not be connected directly to VCC or GND."+ },+ {+ "number": "5",+ "name": "VCC",+ "type": "power_in",+ "description": "Supply pin with a recommended operating range of 1.65 V to 5.5 V; a decoupling capacitor should be placed close to this pin and GND."+ }+ ],+ "provenance": {+ "extractor": "extract_pins 0.3",+ "factory_chain": {+ "factory": "2.0.0",+ "extractor": "extract_pins 0.3",+ "primary_model": "claude-haiku-5-5",+ "primary_mode": "text",+ "consensus_model": "claude-sonnet-5-5",+ "consensus": "agreed",+ "guards": "pin_guards 0.1: passed",+ "guard_notes": [+ "extractor flagged: The ordering addendum (page 20) lists SN74LVC1G32DCK3 as Obsolete with carrier and quantity given as; The Figure 4-1 text extraction is partly scrambled. Pin numbers and names were taken from Table 4-1 "+ ],+ "pages_sent": 20,+ "cost_usd": 0.0986,+ "at": "2026-10-08T20:22:32"+ },+ "datasheet": {+ "url": "https://www.ti.com/cn/lit/gpn/sn74lvc1g32",+ "pages": 51,+ "sha256": "4328a2a798937dad",+ "source_tier": "lcsc"+ },+ "cad": "KiCad official (CC-BY-SA 4.0)",+ "pins": {+ "total": 5,+ "described": 5,+ "cites_pages": true,+ "refuses_to_fabricate": true+ }+ },+ "viewers": {+ "symbol": "viewers/symbol.html",+ "footprint": "viewers/footprint.html"+ },+ "models_3d": [+ {+ "file": "sn74lvc1g32dck3.step",+ "role": "plain",+ "up": "Z",+ "units": "mm",+ "origin": "footprint origin = pad-pattern centre",+ "seat": "z = 0",+ "extents_mm": [+ 2.1,+ 2,+ 1.1+ ],+ "zmin_mm": 0,+ "centre_offset_mm": 0,+ "footprint_binding": "identity",+ "sha256": "2860de5b7b085919ff6e952148353f928798588d9f544dc69430545aff2ba908",+ "checked": "2026-10-08",+ "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"+ },+ {+ "file": "sn74lvc1g32dck3-etched.step",+ "role": "eda",+ "up": "Z",+ "units": "mm",+ "origin": "footprint origin = pad-pattern centre",+ "seat": "z = 0",+ "extents_mm": [+ 2.1,+ 2,+ 1.1+ ],+ "zmin_mm": 0,+ "centre_offset_mm": 0,+ "footprint_binding": "identity",+ "sha256": "8903a113f164d9a5bba905e145e472ff4a48a43d4651eee08b399fcc7a7e7bf1",+ "checked": "2026-10-08",+ "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"+ }+ ]+ },+ "visibility": "public",+ "org": "adom",+ "author": {+ "name": "Ray",+ "email": "[email protected]"+ }+}