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SN74LVC1G3157DCKR-MS

Public Made by Adom

by adom

MSKSEMI Logic Gates, SC-70-6. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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Contents

README

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SN74LVC1G3157DCKR-MS

MSKSEMI · Logic Gates · SC-70-6

SN74LVC1G3157DCKR-MS from MSKSEMI, in a SC-70-6. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 B1 bidirectional Data port B1, connected to A when Select is high.
2 GND power_in Ground.
3 B0 bidirectional Data port B0, connected to A when Select is low.
4 A bidirectional Common data port A, connected to B0 or B1 depending on Select.
5 VCC power_in Power supply port, recommended operating range 1.65 V to 5.5 V.
6 Select input Controlling choice input (L: B0 to A, H: B1 to A); must be held high or low and not float, tolerates up to 7.0 V regardless of VCC.

Key specifications

Parameter Value
Manufacturer MSKSEMI
Package SC-70-6
Category Logic
Pins 6

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Supply Voltage VCC -0.5 7 V 4
DC Switch Voltage VS -0.5 V Upper limit printed as VCC+0.5 V 4
DC Input Voltage VIN -0.5 7 V 4
DC Input Diode Current IIK -50 mA VIN < 0 V 4
DC Output Current Iout 128 mA 4
DC VCC or Ground Current Icc/IGND 100 mA 4
Storage Temperature Range Tstg -65 150 C 4
Junction Temperature Under Bias TJ 150 C 4
Junction Lead Temperature (Soldering) TL 260 C Soldering, 10 seconds 4
Power Dissipation PD 180 mW @ +85 C 4
Supply Voltage Operating VCC 1.65 5.5 V 5
Select Input Voltage VIN 0 V Upper limit printed as VCC 5
Switch Input Voltage VIN 0 V Upper limit printed as VCC 5
Output Voltage VOUT 0 V Upper limit printed as VCC 5
Operating Temperature TA -55 125 C 5
Input Rise and Fall Time, Control Input tr,tf 0 10 ns/V Control input VCC = 2.3 V ~ 3.6 V 5
Input Rise and Fall Time, Control Input tr,tf 0 5 ns/V Control input VCC = 4.5 V ~ 5.5 V 5
Analog Signal Range 0 V Upper limit printed as VCC 6
High Level Input Voltage VIH 1.5 V VCC = 2.3 V ~ 2.8 V 6
High Level Input Voltage VIH 2.4 V VCC = 3 V ~ 4.2 V 6
Low Level Input Voltage VIL 0.4 V VCC = 2.3 V ~ 2.8 V 6
Quiescent Supply Current ICC 1 10 uA VIN = VCC or GND; IOUT = 0; VCC 5.5 V 6
Switch On Resistance RON 3 7 ohm VIN = 0 V, IO = 30 mA; VCC 4.5 V 6
Switch On Resistance RON 5 12 ohm VIN = 2.4 V, IO = -30 mA; VCC 4.5 V 6
Switch On Resistance RON 7 15 ohm VIN = 4.5 V, IO = -30 mA; VCC 4.5 V 6
Switch On Resistance RON 4 9 ohm VIN = 0 V, IO = 24 mA; VCC 3.0 V 6
Switch On Resistance RON 10 20 ohm VIN = 3 V, IO = -24 mA; VCC 3.0 V 6
Switch On Resistance RON 13 30 ohm VIN = 2.3 V, IO = -8 mA; VCC 2.3 V 6
Switch On Resistance RON 6.5 20 ohm VIN = 0 V, IO = 4 mA; VCC 1.65 V 6
Switch On Resistance RON 17 50 ohm VIN = 1.65 V, IO = -4 mA; VCC 1.65 V 6
On Resistance Over Signal Range RRANGE 25 ohm IA = -30 mA; 0 <= VBn <= VCC; VCC 4.5 V 6
On Resistance Over Signal Range RRANGE 50 ohm IA = -24 mA; 0 <= VBn <= VCC; VCC 3 V 6
On Resistance Over Signal Range RRANGE 100 ohm IA = -8 mA; 0 <= VBn <= VCC; VCC 2.3 V 7
On Resistance Over Signal Range RRANGE 300 ohm IA = -4 mA; 0 <= VBn <= VCC; VCC 1.65 V 7
On Resistance Match Between Channels dRON 0.15 ohm IA = -30 mA; VBn = 3.15 V; VCC 4.5 V 7
On Resistance Match Between Channels dRON 0.2 ohm IA = -24 mA; VBn = 2.1 V; VCC 3 V 7
On Resistance Match Between Channels dRON 0.5 ohm IA = -8 mA; VBn = 1.6 V; VCC 2.3 V 7
On Resistance Flatness RFLAT 6 ohm IA = -30 mA; 0 <= VBn <= VCC; VCC 5 V 7
On Resistance Flatness RFLAT 12 ohm IA = -24 mA; 0 <= VBn <= VCC; VCC 3.3 V 7
On Resistance Flatness RFLAT 28 ohm IA = -8 mA; 0 <= VBn <= VCC; VCC 2.5 V 7
On Resistance Flatness RFLAT 125 ohm IA = -4 mA; 0 <= VBn <= VCC; VCC 1.8 V 7
Output Enable Time, Turn On (A to Bn) tPZL tPZL 7 24 nS Figure 1; VI = 2*VCC; VCC 1.65 ~ 1.95 V; TA = -40 C ~ +85 C 7
Output Enable Time, Turn On (A to Bn) tPZL tPZL 3.5 14 nS Figure 1; VI = 2*VCC; VCC 2.3 ~ 2.7 V; TA = -40 C ~ +85 C 7
Output Enable Time, Turn On (A to Bn) tPZL tPZL 2.5 7.6 nS Figure 1; VI = 2*VCC; VCC 3.0 ~ 3.5 V; TA = -40 C ~ +85 C 7
Output Enable Time, Turn On (A to Bn) tPZL tPZL 1.7 5.7 nS Figure 1; VI = 2*VCC; VCC 4.5 ~ 5.5 V; TA = -40 C ~ +85 C 7
Output Disable Time, Turn Off (A to B) tPLZ tPLZ 3 13 nS Figure 1; VI = 2*VCC; VCC 1.65 ~ 1.95 V; TA = -40 C ~ +85 C 7
Output Disable Time, Turn Off (A to B) tPLZ tPLZ 2 7.5 nS Figure 1; VI = 2*VCC; VCC 2.3 ~ 2.7 V; TA = -40 C ~ +85 C 7
Output Disable Time, Turn Off (A to B) tPLZ tPLZ 1.5 5.3 nS Figure 1; VI = 2*VCC; VCC 3.0 ~ 3.5 V; TA = -40 C ~ +85 C 7
Output Disable Time, Turn Off (A to B) tPLZ tPLZ 0.8 3.8 nS Figure 1; VI = 2*VCC; VCC 4.5 ~ 5.5 V; TA = -40 C ~ +85 C 7
Propagation Delay Bus to Bus tPHL, tPLH 1.2 nS Figure 1; VI = OPEN; VCC 2.3 ~ 2.7 V 7
Propagation Delay Bus to Bus tPHL, tPLH 0.8 nS Figure 1; VI = OPEN; VCC 3.0 ~ 3.5 V 7
Propagation Delay Bus to Bus tPHL, tPLH 0.3 nS Figure 1; VI = OPEN; VCC 4.5 ~ 5.5 V 7
Off Isolation OIRR -57 dB Figure 4, RL = 50 ohm, f = 10 MHz; VCC 1.65 ~ 5.5 V 8
Crosstalk Xtalk -54 dB Figure 5, RL = 50 ohm, f = 10 MHz; VCC 1.65 ~ 5.5 V 8
Charge Injection Q 7 pC Figure 3, CL = 0.1 nF, VGEN = 0 V, RGEN = 0 ohm; VCC 5.0 V 8
-3 dB Bandwidth BW 350 MHz Figure 8, RL = 50 ohm; VCC 1.65 ~ 5.5 V 8

CAD (KiCad official)

  • Symbol: SN74LVC1G3157DCKR-MS
  • Footprint: Package_TO_SOT_SMD:SOT-363_SC-70-6
  • 3D model: SC-70-6 (KiCad packages3D, STEP)
  • 3D model files: sn74lvc1g3157dckr-ms-etched.step / sn74lvc1g3157dckr-ms-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); sn74lvc1g3157dckr-ms.step / sn74lvc1g3157dckr-ms.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: MSKSEMI datasheet (15 pp, sha256 46bf36f02bd22f0f, retrieved 2026-10-17, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text+vision), consensus claude-opus-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF