component

SN74LVC1G175DBVR

Public Made by Adom

by adom

SN74LVC1G175DBVR with verified pin map and explicitly nominal drawing-led 3D assets.

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Generated by kicad-footprint-generator · KiCad file format 20260206
Name Last commit message Last updated
docs Retain nominal model correction evidence and exact ordering metadata · John Lauer 24d ago
review Retain nominal model correction evidence and exact ordering metadata · John Lauer 24d ago
viewers Publish 0.1.1 · John Lauer 24d ago
build_nominal_model.py Publish 0.1.1 · John Lauer 24d ago
LICENSE-KICAD.md Publish 0.1.1 · John Lauer 24d ago
package.json Publish 0.1.1 · John Lauer 24d ago
page.json Retain nominal model correction evidence and exact ordering metadata · John Lauer 24d ago
provenance-correction.json Publish 0.1.1 · John Lauer 24d ago
README.md Publish 0.1.1 · John Lauer 24d ago
sn74lvc1g175dbvr-ai-nominal.step Publish 0.1.1 · John Lauer 24d ago
sn74lvc1g175dbvr-etched.check.json Publish 0.1.1 · John Lauer 24d ago
sn74lvc1g175dbvr-etched.check.png Publish 0.1.1 · John Lauer 24d ago
sn74lvc1g175dbvr-etched.fit.json sn74lvc1g175dbvr: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray 1mo ago
sn74lvc1g175dbvr-etched.glb Publish 0.1.1 · John Lauer 24d ago
sn74lvc1g175dbvr-etched.mark-plan.json Publish 0.1.1 · John Lauer 24d ago
sn74lvc1g175dbvr-etched.step Publish 0.1.1 · John Lauer 24d ago
sn74lvc1g175dbvr-hero.glb Publish 0.1.1 · John Lauer 24d ago
sn74lvc1g175dbvr-hero.overlay.json Publish 0.1.1 · John Lauer 24d ago
sn74lvc1g175dbvr.glb Publish 0.1.1 · John Lauer 24d ago
sn74lvc1g175dbvr.kicad_mod Publish 0.1.0 · Ray 1mo ago
sn74lvc1g175dbvr.kicad_sym Publish 0.1.0 · Ray 1mo ago
sn74lvc1g175dbvr.lbr Publish 0.1.0 · Ray 1mo ago
sn74lvc1g175dbvr.step Publish 0.1.1 · John Lauer 24d ago

SN74LVC1G175DBVR

Texas Instruments · 6-pin SOT-23 (DBV0006A).

Pinout

Pin Name Type Function
1 CLK input Clock input. Data on D is transferred to Q on the rising edge of CLK when CLR is high.
2 GND power_in Ground reference (0 V) for the device.
3 D input Data input to the D flip-flop. Sampled on the rising edge of CLK and transferred to Q when CLR is high.
4 Q output Flip-flop output. Reflects the D input latched on the last CLK rising edge; forced low when CLR is asserted low. Drive strength ±24 mA at VCC = 3.3 V.
5 VCC power_in Supply voltage input. Operating range 1.65 V to 5.5 V; inputs accept up to 5.5 V regardless of VCC.
6 CLR input Active-low asynchronous clear input. When CLR is low, Q is forced low regardless of CLK or D; normal operation resumes when CLR is high.

CAD and provenance

The plain and marked STEP/GLB files are original Adom nominal reconstructions from TI's package drawing: 2.9 × 1.6 mm body, 2.9 mm lead span, 0.95 mm pitch and 1.20 mm height. The prior generic model was 1.55 mm tall, above TI's 1.45 mm maximum. Lead bends, mold taper and colors are illustrative; this is not manufacturer CAD or a tolerance envelope.

The marked variant adds a subtle virtual full-MPN identification layer, 0.005 mm above the package. It is neither a factory mark nor a recessed manufacturing feature. Board-use assets exclude the hero's nonphysical footprint and signal overlays.

The existing KiCad-derived symbol and footprint retain their original library terms. The footprint is a generic project-compatible variant; compare its land pattern with the manufacturer example before selecting a process. See correction and provenance, current manufacturer datasheet, and TI source.

Only exact ordering code SN74LVC1G175DBVR is asserted here. Earlier concatenated variant strings were unsupported and have been removed.

Local model inspection and native symbol/footprint validation are separate from physical qualification and published wiki visual review.