SN74LVC1G08DBVR

{
 "schema": "adom.pads/1",
 "slug": "sn74lvc1g08dbvr",
 "footprint": "SOT-23-5",
 "generated_from": {
  "footprint": "SOT-23-5@sha256:455a3f7c3e5eb5b8",
  "pins": "page.json:component.pins",
  "overrides": null
 },
 "pin1": {
  "pad": "1",
  "at": [
   -1.1375,
   -0.95
  ],
  "corner": "top-left",
  "source": "silk-marker",
  "derived_from": "SOT-23-5@sha256:455a3f7c3e5eb5b8"
 },
 "pad_count": 5,
 "symbol_pins": [
  "1",
  "2",
  "3",
  "4",
  "5"
 ],
 "paste_apertures": 0,
 "issues": [],
 "pads": [
  {
   "pad": "1",
   "kind": "smd",
   "shape": "roundrect",
   "at": [
    -1.1375,
    -0.95
   ],
   "rot": 0.0,
   "size": [
    1.325,
    0.6
   ],
   "layers": [
    "F.Cu",
    "F.Mask",
    "F.Paste"
   ],
   "thermal": false,
   "pin": "1",
   "name": "A",
   "type": "input",
   "description": "Logic input A to the 2-input AND gate. CMOS input, VIH ≥ 0.7·VCC (VCC = 3-5.5 V), input leakage ±5 µA max, VI range 0-5.5 V.",
   "is_pin1": true,
   "source": {
    "geometry": "SOT-23-5.kicad_mod",
    "meaning": "page.json:component.pins",
    "correspondence": "kicad: symbol pin number == pad name"
   }
  },
  {
   "pad": "2",
   "kind": "smd",
   "shape": "roundrect",
   "at": [
    -1.1375,
    0.0
   ],
   "rot": 0.0,
   "size": [
    1.325,
    0.6
   ],
   "layers": [
    "F.Cu",
    "F.Mask",
    "F.Paste"
   ],
   "thermal": false,
   "pin": "2",
   "name": "B",
   "type": "input",
   "description": "Logic input B to the 2-input AND gate. CMOS input with the same VIH/VIL thresholds and ±5 µA leakage as input A.",
   "is_pin1": false,
   "source": {
    "geometry": "SOT-23-5.kicad_mod",
    "meaning": "page.json:component.pins",
    "correspondence": "kicad: symbol pin number == pad name"
   }
  },
  {
   "pad": "3",
   "kind": "smd",
   "shape": "roundrect",
   "at": [
    -1.1375,
    0.95
   ],
   "rot": 0.0,
   "size": [
    1.325,
    0.6
   ],
   "layers": [
    "F.Cu",
    "F.Mask",
    "F.Paste"
   ],
   "thermal": false,
   "pin": "3",
   "name": "GND",
   "type": "power_in",
   "description": "Ground reference for the device. Continuous current through VCC or GND is limited to ±100 mA.",
   "is_pin1": false,
   "source": {
    "geometry": "SOT-23-5.kicad_mod",
    "meaning": "page.json:component.pins",
    "correspondence": "kicad: symbol pin number == pad name"
   }
  },
  {
   "pad": "4",
   "kind": "smd",
   "shape": "roundrect",
   "at": [
    1.1375,
    0.95
   ],
   "rot": 0.0,
   "size": [
    1.325,
    0.6
   ],
   "layers": [
    "F.Cu",
    "F.Mask",
    "F.Paste"
   ],
   "thermal": false,
   "pin": "4",
   "name": "Y",
   "type": "output",
   "description": "AND-gate logic output (Y = A·B). Push-pull CMOS output rated ±32 mA at VCC = 4.5 V (VOH ≥ 3.8 V, VOL ≤ 0.55 V); propagation delay tPHL/tPLH ≈ 10 ns typ. with CL = 15 pF.",
   "is_pin1": false,
   "source": {
    "geometry": "SOT-23-5.kicad_mod",
    "meaning": "page.json:component.pins",
    "correspondence": "kicad: symbol pin number == pad name"
   }
  },
  {
   "pad": "5",
   "kind": "smd",
   "shape": "roundrect",
   "at": [
    1.1375,
    -0.95
   ],
   "rot": 0.0,
   "size": [
    1.325,
    0.6
   ],
   "layers": [
    "F.Cu",
    "F.Mask",
    "F.Paste"
   ],
   "thermal": false,
   "pin": "5",
   "name": "VCC",
   "type": "power_in",
   "description": "Positive supply voltage. Operating range 1.65 V to 5.5 V (abs. max 6.5 V); quiescent ICC ≤ 10 µA. Bypass with a 0.1 µF capacitor to GND close to the pin.",
   "is_pin1": false,
   "source": {
    "geometry": "SOT-23-5.kicad_mod",
    "meaning": "page.json:component.pins",
    "correspondence": "kicad: symbol pin number == pad name"
   }
  }
 ]
}