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Set visibility: public

Ray ·85b864d000 · ·parent 229cd4c
1 file changed +9−6
page.json+9−6
@@ -32,31 +32,31 @@         "number": "1",         "name": "A",         "type": "input",-        "description": "Logic input A to the 2-input AND gate. CMOS input, VIH \u2265 0.7\u00b7VCC (VCC = 3-5.5 V), input leakage \u00b15 \u00b5A max, VI range 0-5.5 V."+        "description": "Logic input A to the 2-input AND gate. CMOS input, VIH ≥ 0.7·VCC (VCC = 3-5.5 V), input leakage ±5 µA max, VI range 0-5.5 V."       },       {         "number": "2",         "name": "B",         "type": "input",-        "description": "Logic input B to the 2-input AND gate. CMOS input with the same VIH/VIL thresholds and \u00b15 \u00b5A leakage as input A."+        "description": "Logic input B to the 2-input AND gate. CMOS input with the same VIH/VIL thresholds and ±5 µA leakage as input A."       },       {         "number": "3",         "name": "GND",         "type": "power_in",-        "description": "Ground reference for the device. Continuous current through VCC or GND is limited to \u00b1100 mA."+        "description": "Ground reference for the device. Continuous current through VCC or GND is limited to ±100 mA."       },       {         "number": "4",         "name": "Y",         "type": "output",-        "description": "AND-gate logic output (Y = A\u00b7B). Push-pull CMOS output rated \u00b132 mA at VCC = 4.5 V (VOH \u2265 3.8 V, VOL \u2264 0.55 V); propagation delay tPHL/tPLH \u2248 10 ns typ. with CL = 15 pF."+        "description": "AND-gate logic output (Y = A·B). Push-pull CMOS output rated ±32 mA at VCC = 4.5 V (VOH ≥ 3.8 V, VOL ≤ 0.55 V); propagation delay tPHL/tPLH ≈ 10 ns typ. with CL = 15 pF."       },       {         "number": "5",         "name": "VCC",         "type": "power_in",-        "description": "Positive supply voltage. Operating range 1.65 V to 5.5 V (abs. max 6.5 V); quiescent ICC \u2264 10 \u00b5A. Bypass with a 0.1 \u00b5F capacitor to GND close to the pin."+        "description": "Positive supply voltage. Operating range 1.65 V to 5.5 V (abs. max 6.5 V); quiescent ICC ≤ 10 µA. Bypass with a 0.1 µF capacitor to GND close to the pin."       }     ],     "provenance": {@@ -120,5 +120,8 @@     "docs/sn74lvc1g08dbvr-datasheet.pdf",     "viewers/symbol.html",     "viewers/footprint.html"-  ]+  ],+  "visibility": {+    "public": true+  } }\ No newline at end of file