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sn74lvc1g08dbvr: factory component page (tier=lcsc)

Ray ·229cd4c145 · ·parent 13e69a0
3 files changed +14−17
README.md+4−4
@@ -1,8 +1,8 @@ # SN74LVC1G08DBVR -**UMW** · Gates · SOT-23-5+**Texas Instruments** · Gates · SOT-23-5 -SN74LVC1G08DBVR from UMW, in a SOT-23-5. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.+SN74LVC1G08DBVR from Texas Instruments, in a SOT-23-5. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.  ## Pinout @@ -18,7 +18,7 @@ SN74LVC1G08DBVR from UMW, in a SOT-23-5. Pinout and pin descriptions extracted f  | Parameter | Value | |---|---|-| Manufacturer | UMW |+| Manufacturer | Texas Instruments | | Package | SOT-23-5 | | Category | Logic | | Pins | 5 |@@ -47,7 +47,7 @@ SN74LVC1G08DBVR from UMW, in a SOT-23-5. Pinout and pin descriptions extracted f  Data extracted from the manufacturer datasheet, not a distributor listing: -- **Datasheet:** [UMW datasheet](docs/sn74lvc1g08dbvr-datasheet.pdf) (15 pp, sha256 `d96a313b6463337a`, retrieved 2026-08-17, tier: lcsc)+- **Datasheet:** [Texas Instruments datasheet](docs/sn74lvc1g08dbvr-datasheet.pdf) (15 pp, sha256 `d96a313b6463337a`, retrieved 2026-08-17, tier: lcsc) - **Extractor:** `ds2sf` (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate. - **CAD:** KiCad official libraries (CC-BY-SA 4.0). 
docs/hero.png
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page.json+10−13
@@ -3,7 +3,7 @@   "type": "component",   "slug": "sn74lvc1g08dbvr",   "title": "SN74LVC1G08DBVR",-  "brief": "UMW Gates, SOT-23-5. Datasheet-verified pinout, KiCad symbol/footprint/3D.",+  "brief": "Texas Instruments Gates, SOT-23-5. Datasheet-verified pinout, KiCad symbol/footprint/3D.",   "version": "0.1.0",   "license": "CC-BY-SA-4.0",   "tags": [@@ -13,7 +13,7 @@   ],   "component": {     "mpn": "SN74LVC1G08DBVR",-    "manufacturer": "UMW",+    "manufacturer": "Texas Instruments",     "package": "SOT-23-5",     "pin_count": 5,     "category": "Logic",@@ -32,31 +32,31 @@         "number": "1",         "name": "A",         "type": "input",-        "description": "Logic input A to the 2-input AND gate. CMOS input, VIH ≥ 0.7·VCC (VCC = 3-5.5 V), input leakage ±5 µA max, VI range 0-5.5 V."+        "description": "Logic input A to the 2-input AND gate. CMOS input, VIH \u2265 0.7\u00b7VCC (VCC = 3-5.5 V), input leakage \u00b15 \u00b5A max, VI range 0-5.5 V."       },       {         "number": "2",         "name": "B",         "type": "input",-        "description": "Logic input B to the 2-input AND gate. CMOS input with the same VIH/VIL thresholds and ±5 µA leakage as input A."+        "description": "Logic input B to the 2-input AND gate. CMOS input with the same VIH/VIL thresholds and \u00b15 \u00b5A leakage as input A."       },       {         "number": "3",         "name": "GND",         "type": "power_in",-        "description": "Ground reference for the device. Continuous current through VCC or GND is limited to ±100 mA."+        "description": "Ground reference for the device. Continuous current through VCC or GND is limited to \u00b1100 mA."       },       {         "number": "4",         "name": "Y",         "type": "output",-        "description": "AND-gate logic output (Y = A·B). Push-pull CMOS output rated ±32 mA at VCC = 4.5 V (VOH ≥ 3.8 V, VOL ≤ 0.55 V); propagation delay tPHL/tPLH ≈ 10 ns typ. with CL = 15 pF."+        "description": "AND-gate logic output (Y = A\u00b7B). Push-pull CMOS output rated \u00b132 mA at VCC = 4.5 V (VOH \u2265 3.8 V, VOL \u2264 0.55 V); propagation delay tPHL/tPLH \u2248 10 ns typ. with CL = 15 pF."       },       {         "number": "5",         "name": "VCC",         "type": "power_in",-        "description": "Positive supply voltage. Operating range 1.65 V to 5.5 V (abs. max 6.5 V); quiescent ICC ≤ 10 µA. Bypass with a 0.1 µF capacitor to GND close to the pin."+        "description": "Positive supply voltage. Operating range 1.65 V to 5.5 V (abs. max 6.5 V); quiescent ICC \u2264 10 \u00b5A. Bypass with a 0.1 \u00b5F capacitor to GND close to the pin."       }     ],     "provenance": {@@ -82,7 +82,7 @@   },   "metadata": {     "specs": {-      "Manufacturer": "UMW",+      "Manufacturer": "Texas Instruments",       "Package": "SOT-23-5",       "Category": "Logic",       "Pins": "5"@@ -98,7 +98,7 @@   "discovery_triggers": [     "sn74lvc1g08dbvr"   ],-  "discovery_pitch": "SN74LVC1G08DBVR (UMW) component page with datasheet-verified CAD.",+  "discovery_pitch": "SN74LVC1G08DBVR (Texas Instruments) component page with datasheet-verified CAD.",   "author": {     "name": "Ray",     "email": "[email protected]"@@ -120,8 +120,5 @@     "docs/sn74lvc1g08dbvr-datasheet.pdf",     "viewers/symbol.html",     "viewers/footprint.html"-  ],-  "visibility": {-    "public": true-  }+  ] }\ No newline at end of file