# SN74LVC1G08DBVR-JSM

**JSMSEMI** · Gates · SOT-23-5

SN74LVC1G08DBVR-JSM from JSMSEMI, in a SOT-23-5. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | A | input | Input A of the 2-input AND gate; accepts voltages up to 5.5 V and must be held at VCC or GND if unused. |
| 2 | B | input | Input B of the 2-input AND gate; accepts voltages up to 5.5 V and must be held at VCC or GND if unused. |
| 3 | GND | power_in | Ground pin. |
| 4 | Y | output | Gate output Y = A AND B, with ±24 mA drive at 3 V. |
| 5 | VCC | power_in | Power supply pin, 1.65 V to 5.5 V operating range. |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | JSMSEMI |
| Package | SOT-23-5 |
| Category | Logic |
| Pins | 5 |

## CAD (KiCad official)

- Symbol: `SN74LVC1G08DBVR-JSM`
- Footprint: `Package_TO_SOT_SMD:SOT-23-5`
- 3D model: SOT-23-5 (KiCad packages3D, STEP)
- 3D model files: `sn74lvc1g08dbvr-jsm-etched.step` / `sn74lvc1g08dbvr-jsm-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `sn74lvc1g08dbvr-jsm.step` / `sn74lvc1g08dbvr-jsm.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [JSMSEMI datasheet](docs/sn74lvc1g08dbvr-jsm-datasheet.pdf) (10 pp, sha256 `e4d6cea5b80b3a4f`, retrieved 2026-10-22, tier: lcsc)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-sonnet-5-5` (vision), consensus `claude-opus-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/sn74lvc1g08dbvr-jsm-datasheet.pdf)