component
SN74LVC1G00MDCKREP
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Texas Instruments Logic Gates, SC-70-5. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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README.mdadded+41@@ -0,0 +1,41 @@+# SN74LVC1G00MDCKREP++**Texas Instruments** · Logic Gates · SC-70-5++SN74LVC1G00MDCKREP from Texas Instruments, in a SC-70-5. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.++## Pinout++| Pin | Name | Type | Function |+|---|---|---|---|+| 1 | A | input | Input A to the 2-input NAND gate; accepts input voltages from 0 to 5.5V per recommended operating conditions. |+| 2 | B | input | Input B to the 2-input NAND gate; accepts input voltages from 0 to 5.5V per recommended operating conditions. |+| 3 | GND | power_in | Ground connection; reference potential for the device. |+| 4 | Y | output | Output of the 2-input NAND gate performing the Boolean function Y = A·B in positive logic; output voltage range 0 to VCC. |+| 5 | VCC | power_in | Supply voltage for the device; recommended operating range 1.65V to 5.5V. |++## Key specifications++| Parameter | Value |+|---|---|+| Manufacturer | Texas Instruments |+| Package | SC-70-5 |+| Category | Logic |+| Pins | 5 |++## CAD (KiCad official)++- Symbol: `SN74LVC1G00MDCKREP`+- Footprint: `Package_TO_SOT_SMD:SOT-353_SC-70-5`+- 3D model: SC-70-5 (KiCad packages3D, STEP)+- 3D model files: `sn74lvc1g00mdckrep-etched.step` / `sn74lvc1g00mdckrep-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `sn74lvc1g00mdckrep.step` / `sn74lvc1g00mdckrep.glb` are the bare package body.++## Provenance++Data extracted from the manufacturer datasheet, not a distributor listing:++- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/cn/lit/gpn/sn74lvc1g00-ep) (17 pp, sha256 `0cfe4a7af73d5de6`, retrieved 2026-10-03, tier: lcsc)+- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-4-5-20251001` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.+- **CAD:** KiCad official libraries (CC-BY-SA 4.0).++[Datasheet PDF](docs/sn74lvc1g00mdckrep-datasheet.pdf)
page.jsonadded+141@@ -0,0 +1,141 @@+{+ "slug": "sn74lvc1g00mdckrep",+ "version": "0.1.0",+ "type": "component",+ "description": "Texas Instruments Logic Gates, SC-70-5. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.",+ "tags": [+ "component",+ "logic",+ "sn74lvc1g00mdckrep",+ "factory-2.0.0",+ "extractor-text"+ ],+ "dependencies": {},+ "hero": {+ "type": "image",+ "path": "docs/hero.png"+ },+ "files": [+ "page.json",+ "README.md",+ "sn74lvc1g00mdckrep.kicad_sym",+ "sn74lvc1g00mdckrep.kicad_mod",+ "sn74lvc1g00mdckrep.glb",+ "sn74lvc1g00mdckrep.step",+ "sn74lvc1g00mdckrep.lbr",+ "docs/hero.png",+ "docs/sn74lvc1g00mdckrep-datasheet.pdf",+ "viewers/symbol.html",+ "viewers/footprint.html",+ "sn74lvc1g00mdckrep-hero.glb",+ "sn74lvc1g00mdckrep-hero.overlay.json"+ ],+ "component": {+ "mpn": "SN74LVC1G00MDCKREP",+ "manufacturer": "Texas Instruments",+ "package": "SC-70-5",+ "pin_count": 5,+ "category": "Logic",+ "subcategory": "Logic Gates",+ "datasheet": "https://www.ti.com/cn/lit/gpn/sn74lvc1g00-ep",+ "parts": {+ "symbol": "sn74lvc1g00mdckrep.kicad_sym",+ "footprint": "sn74lvc1g00mdckrep.kicad_mod",+ "model_3d": "sn74lvc1g00mdckrep-hero.glb",+ "model_3d_plain": "sn74lvc1g00mdckrep.glb",+ "model_3d_step": "sn74lvc1g00mdckrep-etched.step",+ "model_3d_step_plain": "sn74lvc1g00mdckrep.step",+ "lbr": "sn74lvc1g00mdckrep.lbr"+ },+ "distributor_links": {+ "lcsc": 2860535,+ "digikey": "296-22339-2-ND",+ "mouser": "595-SN74LVC00MDCKREP"+ },+ "distributor_check": {+ "checked_at": "2026-10-03T08:46:19Z",+ "source": "Component Ocean /api/assign-pns",+ "digikey": {+ "pn": "296-22339-2-ND",+ "status": "found"+ },+ "mouser": {+ "pn": "595-SN74LVC00MDCKREP",+ "status": "found"+ }+ },+ "pins": [+ {+ "number": "1",+ "name": "A",+ "type": "input",+ "description": "Input A to the 2-input NAND gate; accepts input voltages from 0 to 5.5V per recommended operating conditions."+ },+ {+ "number": "2",+ "name": "B",+ "type": "input",+ "description": "Input B to the 2-input NAND gate; accepts input voltages from 0 to 5.5V per recommended operating conditions."+ },+ {+ "number": "3",+ "name": "GND",+ "type": "power_in",+ "description": "Ground connection; reference potential for the device."+ },+ {+ "number": "4",+ "name": "Y",+ "type": "output",+ "description": "Output of the 2-input NAND gate performing the Boolean function Y = A·B in positive logic; output voltage range 0 to VCC."+ },+ {+ "number": "5",+ "name": "VCC",+ "type": "power_in",+ "description": "Supply voltage for the device; recommended operating range 1.65V to 5.5V."+ }+ ],+ "provenance": {+ "extractor": "extract_pins 0.3",+ "factory_chain": {+ "factory": "2.0.0",+ "extractor": "extract_pins 0.3",+ "primary_model": "claude-haiku-4-5-20251001",+ "primary_mode": "text",+ "consensus_model": "claude-sonnet-5-5",+ "consensus": "agreed",+ "guards": "pin_guards 0.1: passed",+ "guard_notes": [+ "extractor flagged: Exact pin numbering for SC-70 package was inferred from standard TI conventions and package orientat"+ ],+ "pages_sent": 17,+ "cost_usd": 0.1095,+ "at": "2026-10-03T08:45:58"+ },+ "datasheet": {+ "url": "https://www.ti.com/cn/lit/gpn/sn74lvc1g00-ep",+ "pages": 17,+ "sha256": "0cfe4a7af73d5de6",+ "source_tier": "lcsc"+ },+ "cad": "KiCad official (CC-BY-SA 4.0)",+ "pins": {+ "total": 5,+ "described": 5,+ "cites_pages": true,+ "refuses_to_fabricate": true+ }+ },+ "viewers": {+ "symbol": "viewers/symbol.html",+ "footprint": "viewers/footprint.html"+ }+ },+ "visibility": "public",+ "org": "adom",+ "author": {+ "name": "Ray",+ "email": "[email protected]"+ }+}