SN74LVC1G00DCKT

{
  "slug": "sn74lvc1g00dckt",
  "version": "0.1.0",
  "type": "component",
  "description": "Texas Instruments Logic Gates, SC-70-5. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.",
  "tags": [
    "component",
    "logic",
    "sn74lvc1g00dckt",
    "factory-2.0.0",
    "extractor-text"
  ],
  "dependencies": {},
  "hero": {
    "type": "image",
    "path": "docs/hero.png"
  },
  "files": [
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    "README.md",
    "sn74lvc1g00dckt.kicad_sym",
    "sn74lvc1g00dckt.kicad_mod",
    "sn74lvc1g00dckt.glb",
    "sn74lvc1g00dckt.step",
    "sn74lvc1g00dckt.lbr",
    "docs/hero.png",
    "docs/sn74lvc1g00dckt-datasheet.pdf",
    "viewers/symbol.html",
    "viewers/footprint.html",
    "sn74lvc1g00dckt-hero.glb",
    "sn74lvc1g00dckt-hero.overlay.json"
  ],
  "component": {
    "mpn": "SN74LVC1G00DCKT",
    "manufacturer": "Texas Instruments",
    "package": "SC-70-5",
    "pin_count": 5,
    "category": "Logic",
    "subcategory": "Logic Gates",
    "datasheet": "https://www.ti.com/cn/lit/gpn/sn74lvc1g00",
    "parts": {
      "symbol": "sn74lvc1g00dckt.kicad_sym",
      "footprint": "sn74lvc1g00dckt.kicad_mod",
      "model_3d": "sn74lvc1g00dckt-hero.glb",
      "model_3d_plain": "sn74lvc1g00dckt.glb",
      "model_3d_step": "sn74lvc1g00dckt-etched.step",
      "model_3d_step_plain": "sn74lvc1g00dckt.step",
      "lbr": "sn74lvc1g00dckt.lbr"
    },
    "distributor_links": {
      "lcsc": "C2878883",
      "digikey": "296-26587-2-ND",
      "mouser": "595-SN74LVC1G00DCKT"
    },
    "distributor_check": {
      "checked_at": "2026-10-11T15:00:54Z",
      "source": "Component Ocean /api/assign-pns",
      "digikey": {
        "pn": "296-26587-2-ND",
        "status": "found"
      },
      "mouser": {
        "pn": "595-SN74LVC1G00DCKT",
        "status": "found"
      }
    },
    "pins": [
      {
        "number": "1",
        "name": "A",
        "type": "input",
        "description": "Logic input A of the 2-input NAND gate; recommended input voltage range is 0 V to 5.5 V and it must not be left floating."
      },
      {
        "number": "2",
        "name": "B",
        "type": "input",
        "description": "Logic input B of the 2-input NAND gate; recommended input voltage range is 0 V to 5.5 V and it must not be left floating."
      },
      {
        "number": "3",
        "name": "GND",
        "type": "power_in",
        "description": "Ground reference; it must sink the total output current plus the maximum supply current ICC, and the absolute maximum continuous current through GND is ±100 mA."
      },
      {
        "number": "4",
        "name": "Y",
        "type": "output",
        "description": "Balanced CMOS push-pull output providing Y = A•B (NAND); recommended output current is ±24 mA at VCC = 3 V and the absolute maximum continuous output current is ±50 mA."
      },
      {
        "number": "5",
        "name": "VCC",
        "type": "power_in",
        "description": "Supply pin with an operating range of 1.65 V to 5.5 V (absolute maximum 6.5 V), which should be decoupled with a 0.1 µF capacitor close to the pin."
      }
    ],
    "provenance": {
      "extractor": "extract_pins 0.3",
      "factory_chain": {
        "factory": "2.0.0",
        "extractor": "extract_pins 0.3",
        "primary_model": "claude-haiku-5-5",
        "primary_mode": "text",
        "consensus_model": "claude-sonnet-5-5",
        "consensus": "agreed",
        "guards": "pin_guards 0.1: passed",
        "guard_notes": [
          "extractor flagged: The DCK pin diagram text in the extracted datasheet is garbled. Pin assignments were taken from the ; The pin-function table has no DCK-specific description text. Pin descriptions were built from the re; The NC (no internal connection) entry in the pin table does not apply to the DCK package, so no NC p"
        ],
        "pages_sent": 17,
        "cost_usd": 0.0805,
        "at": "2026-10-11T15:00:39"
      },
      "datasheet": {
        "url": "https://www.ti.com/cn/lit/gpn/sn74lvc1g00",
        "pages": 50,
        "sha256": "400ba447eb6ea399",
        "source_tier": "lcsc"
      },
      "cad": "KiCad official (CC-BY-SA 4.0)",
      "pins": {
        "total": 5,
        "described": 5,
        "cites_pages": true,
        "refuses_to_fabricate": true
      }
    },
    "viewers": {
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      "footprint": "viewers/footprint.html"
    },
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        "role": "plain",
        "up": "Z",
        "units": "mm",
        "origin": "footprint origin = pad-pattern centre",
        "seat": "z = 0",
        "extents_mm": [
          2.1,
          2.0,
          1.1
        ],
        "zmin_mm": 0.0,
        "centre_offset_mm": 0.0,
        "footprint_binding": "identity",
        "sha256": "2860de5b7b085919ff6e952148353f928798588d9f544dc69430545aff2ba908",
        "checked": "2026-10-11",
        "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"
      },
      {
        "file": "sn74lvc1g00dckt-etched.step",
        "role": "eda",
        "up": "Z",
        "units": "mm",
        "origin": "footprint origin = pad-pattern centre",
        "seat": "z = 0",
        "extents_mm": [
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          1.1
        ],
        "zmin_mm": 0.0,
        "centre_offset_mm": 0.0,
        "footprint_binding": "identity",
        "sha256": "85077379152034ad77172be16ee91099a1da1785d964200f7d701109e45dc113",
        "checked": "2026-10-11",
        "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"
      }
    ]
  }
}