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SN74LVC1G00DCKT
Public Made by Adomby adom
Texas Instruments Logic Gates, SC-70-5. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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SN74LVC1G00DCKT
Texas Instruments · Logic Gates · SC-70-5
SN74LVC1G00DCKT from Texas Instruments, in a SC-70-5. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | A | input | Logic input A of the 2-input NAND gate; recommended input voltage range is 0 V to 5.5 V and it must not be left floating. |
| 2 | B | input | Logic input B of the 2-input NAND gate; recommended input voltage range is 0 V to 5.5 V and it must not be left floating. |
| 3 | GND | power_in | Ground reference; it must sink the total output current plus the maximum supply current ICC, and the absolute maximum continuous current through GND is ±100 mA. |
| 4 | Y | output | Balanced CMOS push-pull output providing Y = A•B (NAND); recommended output current is ±24 mA at VCC = 3 V and the absolute maximum continuous output current is ±50 mA. |
| 5 | VCC | power_in | Supply pin with an operating range of 1.65 V to 5.5 V (absolute maximum 6.5 V), which should be decoupled with a 0.1 µF capacitor close to the pin. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | SC-70-5 |
| Category | Logic |
| Pins | 5 |
CAD (KiCad official)
- Symbol:
SN74LVC1G00DCKT - Footprint:
Package_TO_SOT_SMD:SOT-353_SC-70-5 - 3D model: SC-70-5 (KiCad packages3D, STEP)
- 3D model files:
sn74lvc1g00dckt-etched.step/sn74lvc1g00dckt-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);sn74lvc1g00dckt.step/sn74lvc1g00dckt.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (50 pp, sha256
400ba447eb6ea399, retrieved 2026-10-11, tier: lcsc) - Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# SN74LVC1G00DCKT
**Texas Instruments** · Logic Gates · SC-70-5
SN74LVC1G00DCKT from Texas Instruments, in a SC-70-5. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | A | input | Logic input A of the 2-input NAND gate; recommended input voltage range is 0 V to 5.5 V and it must not be left floating. |
| 2 | B | input | Logic input B of the 2-input NAND gate; recommended input voltage range is 0 V to 5.5 V and it must not be left floating. |
| 3 | GND | power_in | Ground reference; it must sink the total output current plus the maximum supply current ICC, and the absolute maximum continuous current through GND is ±100 mA. |
| 4 | Y | output | Balanced CMOS push-pull output providing Y = A•B (NAND); recommended output current is ±24 mA at VCC = 3 V and the absolute maximum continuous output current is ±50 mA. |
| 5 | VCC | power_in | Supply pin with an operating range of 1.65 V to 5.5 V (absolute maximum 6.5 V), which should be decoupled with a 0.1 µF capacitor close to the pin. |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | SC-70-5 |
| Category | Logic |
| Pins | 5 |
## CAD (KiCad official)
- Symbol: `SN74LVC1G00DCKT`
- Footprint: `Package_TO_SOT_SMD:SOT-353_SC-70-5`
- 3D model: SC-70-5 (KiCad packages3D, STEP)
- 3D model files: `sn74lvc1g00dckt-etched.step` / `sn74lvc1g00dckt-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `sn74lvc1g00dckt.step` / `sn74lvc1g00dckt.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/cn/lit/gpn/sn74lvc1g00) (50 pp, sha256 `400ba447eb6ea399`, retrieved 2026-10-11, tier: lcsc)
- **Datasheet language:** Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/sn74lvc1g00dckt-datasheet.pdf)