SN74LVC16646ADLR from Texas Instruments, in a SSOP-56-300mil. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	1DIR	input	Direction control for the first 8-bit transceiver; determines which bus receives data when 1OE is low.
2	1CLKAB	input	Clock for the first-channel A-to-B register; data is stored on the low-to-high transition.
3	1SAB	input	Select control for the first channel that multiplexes real-time and stored A data to the B bus.
4	GND	power_in	Ground.
5	1A1	bidirectional	First-channel A-port data I/O 1, accepts inputs up to 5.5 V.
6	1A2	bidirectional	First-channel A-port data I/O 2, accepts inputs up to 5.5 V.
7	VCC	power_in	Supply voltage, 1.65 V to 3.6 V operating.
8	1A3	bidirectional	First-channel A-port data I/O 3, accepts inputs up to 5.5 V.
9	1A4	bidirectional	First-channel A-port data I/O 4, accepts inputs up to 5.5 V.
10	1A5	bidirectional	First-channel A-port data I/O 5, accepts inputs up to 5.5 V.
11	GND	power_in	Ground.
12	1A6	bidirectional	First-channel A-port data I/O 6, accepts inputs up to 5.5 V.
13	1A7	bidirectional	First-channel A-port data I/O 7, accepts inputs up to 5.5 V.
14	1A8	bidirectional	First-channel A-port data I/O 8, accepts inputs up to 5.5 V.
15	2A1	bidirectional	Second-channel A-port data I/O 1, accepts inputs up to 5.5 V.
16	2A2	bidirectional	Second-channel A-port data I/O 2, accepts inputs up to 5.5 V.
17	2A3	bidirectional	Second-channel A-port data I/O 3, accepts inputs up to 5.5 V.
18	GND	power_in	Ground.
19	2A4	bidirectional	Second-channel A-port data I/O 4, accepts inputs up to 5.5 V.
20	2A5	bidirectional	Second-channel A-port data I/O 5, accepts inputs up to 5.5 V.
21	2A6	bidirectional	Second-channel A-port data I/O 6, accepts inputs up to 5.5 V.
22	VCC	power_in	Supply voltage, 1.65 V to 3.6 V operating.
23	2A7	bidirectional	Second-channel A-port data I/O 7, accepts inputs up to 5.5 V.
24	2A8	bidirectional	Second-channel A-port data I/O 8, accepts inputs up to 5.5 V.
25	GND	power_in	Ground.
26	2SAB	input	Select control for the second channel that multiplexes real-time and stored A data to the B bus.
27	2CLKAB	input	Clock for the second-channel A-to-B register; data is stored on the low-to-high transition.
28	2DIR	input	Direction control for the second 8-bit transceiver; determines which bus receives data when 2OE is low.
29	2OE	input	Output enable for the second channel; high selects isolation mode, and it should be tied to VCC through a pullup resistor to ensure high impedance during power up or down.
30	2CLKBA	input	Clock for the second-channel B-to-A register; data is stored on the low-to-high transition.
31	2SBA	input	Select control for the second channel that multiplexes real-time and stored B data to the A bus.
32	GND	power_in	Ground.
33	2B8	bidirectional	Second-channel B-port data I/O 8, accepts inputs up to 5.5 V.
34	2B7	bidirectional	Second-channel B-port data I/O 7, accepts inputs up to 5.5 V.
35	VCC	power_in	Supply voltage, 1.65 V to 3.6 V operating.
36	2B6	bidirectional	Second-channel B-port data I/O 6, accepts inputs up to 5.5 V.
37	2B5	bidirectional	Second-channel B-port data I/O 5, accepts inputs up to 5.5 V.
38	2B4	bidirectional	Second-channel B-port data I/O 4, accepts inputs up to 5.5 V.
39	GND	power_in	Ground.
40	2B3	bidirectional	Second-channel B-port data I/O 3, accepts inputs up to 5.5 V.
41	2B2	bidirectional	Second-channel B-port data I/O 2, accepts inputs up to 5.5 V.
42	2B1	bidirectional	Second-channel B-port data I/O 1, accepts inputs up to 5.5 V.
43	1B8	bidirectional	First-channel B-port data I/O 8, accepts inputs up to 5.5 V.
44	1B7	bidirectional	First-channel B-port data I/O 7, accepts inputs up to 5.5 V.
45	1B6	bidirectional	First-channel B-port data I/O 6, accepts inputs up to 5.5 V.
46	GND	power_in	Ground.
47	1B5	bidirectional	First-channel B-port data I/O 5, accepts inputs up to 5.5 V.
48	1B4	bidirectional	First-channel B-port data I/O 4, accepts inputs up to 5.5 V.
49	1B3	bidirectional	First-channel B-port data I/O 3, accepts inputs up to 5.5 V.
50	VCC	power_in	Supply voltage, 1.65 V to 3.6 V operating.
51	1B2	bidirectional	First-channel B-port data I/O 2, accepts inputs up to 5.5 V.
52	1B1	bidirectional	First-channel B-port data I/O 1, accepts inputs up to 5.5 V.
53	GND	power_in	Ground.
54	1SBA	input	Select control for the first channel that multiplexes real-time and stored B data to the A bus.
55	1CLKBA	input	Clock for the first-channel B-to-A register; data is stored on the low-to-high transition.
56	1OE	input	Output enable for the first channel; high selects isolation mode, and it should be tied to VCC through a pullup resistor to ensure high impedance during power up or down.

Key specifications

Parameter	Value
Manufacturer	Texas Instruments
Package	SSOP-56-300mil
Category	Logic ICs
Pins	56

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter	Symbol	Min	Typ	Max	Unit	Conditions	Page
High-level output voltage	VOH	1.2			V	IOH = -4 mA, VCC = 1.65 V	6
High-level output voltage	VOH	1.7			V	IOH = -8 mA, VCC = 2.3 V	6
High-level output voltage	VOH	2.2			V	IOH = -12 mA, VCC = 2.7 V	6
High-level output voltage	VOH	2.4			V	IOH = -12 mA, VCC = 3 V	6
Low-level output voltage	VOL			0.2	V	IOL = 100 µA, VCC = 1.65 V to 3.6 V	6
Low-level output voltage	VOL			0.45	V	IOL = 4 mA, VCC = 1.65 V	6
Low-level output voltage	VOL			0.7	V	IOL = 8 mA, VCC = 2.3 V	6
Low-level output voltage	VOL			0.4	V	IOL = 12 mA, VCC = 2.7 V	6
Low-level output voltage	VOL			0.55	V	IOL = 24 mA, VCC = 3 V	6
Input current, control inputs	II	-5		5	µA	VI = 0 to 5.5 V, VCC = 3.6 V	6
Power-off leakage current	Ioff	-10		10	µA	VI or VO = 5.5 V, VCC = 0	6
Off-state output current	IOZ	-10		10	µA	VO = 0 to 5.5 V, VCC = 3.6 V	6
Supply current	ICC			20	µA	VI = VCC or GND, IO = 0, VCC = 3.6 V	6
Change in supply current	∆ICC			500	µA	One input at VCC, 0.6 V, other inputs at VCC or GND, VCC = 2.7 V to 3.6 V	6
Input capacitance, control inputs	Ci		5		pF	VI = VCC or GND, VCC = 3.3 V	6
I/O capacitance, A or B ports	Cio		8.5		pF	VO = VCC or GND, VCC = 3.3 V	6
Supply voltage range	VCC	-0.5		6.5	V		5
Input voltage range	VI	-0.5		6.5	V		5
Output voltage range, high-impedance or power-off state	VO	-0.5		6.5	V		5
Output voltage range, high or low state	VO	-0.5			V	max VCC + 0.5 V	5
Input clamp current	IIK	-50			mA	VI < 0	5
Output clamp current	IOK	-50			mA	VO < 0	5
Continuous output current	IO	-50		50	mA		5
Continuous current through each VCC or GND		-100		100	mA		5
Package thermal impedance	θJA		56		°C/W	DL package	5
Storage temperature range	Tstg	-65		150	°C		5
Supply voltage, operating	VCC	1.65		3.6	V	Operating	5
High-level input voltage	VIH	1.7			V	VCC = 2.3 V to 2.7 V	5
High-level input voltage	VIH	2			V	VCC = 2.7 V to 3.6 V	5
Low-level input voltage	VIL			0.7	V	VCC = 2.3 V to 2.7 V	5
Low-level input voltage	VIL			0.8	V	VCC = 2.7 V to 3.6 V	5
Input voltage	VI	0		5.5	V		5
Output voltage, 3-state	VO	0		5.5	V	3-state	5
Output voltage, high or low state	VO	0			V	High or low state, max VCC	5
High-level output current	IOH	-4			mA	VCC = 1.65 V	5
High-level output current	IOH	-8			mA	VCC = 2.3 V	5
High-level output current	IOH	-12			mA	VCC = 2.7 V	5
High-level output current	IOH	-24			mA	VCC = 3 V	5
Low-level output current	IOL			4	mA	VCC = 1.65 V	5
Low-level output current	IOL			8	mA	VCC = 2.3 V	5
Low-level output current	IOL			12	mA	VCC = 2.7 V	5
Low-level output current	IOL			24	mA	VCC = 3 V	5
Input transition rise or fall rate	∆t/∆v			10	ns/V		5
Operating free-air temperature	TA	-40		85	°C		5
Clock frequency	fclock			150	MHz	VCC = 3.3 V ± 0.3 V	6
Pulse duration, CLK high or low	tw	3.3			ns	VCC = 3.3 V ± 0.3 V	6
Setup time, A or B before CLKAB↑ or CLKBA↑	tsu	2.7			ns	VCC = 3.3 V ± 0.3 V	6
Hold time, A or B after CLKAB↑ or CLKBA↑	th	0.3			ns	VCC = 3.3 V ± 0.3 V	6
Maximum frequency	fmax	150			MHz	VCC = 3.3 V ± 0.3 V	7
Propagation delay, A or B to B or A	tpd	0.5		5.2	ns	VCC = 3.3 V ± 0.3 V	7
Propagation delay, CLKAB or CLKBA to A or B	tpd	1.8		6	ns	VCC = 3.3 V ± 0.3 V	7
Propagation delay, SAB or SBA to A or B	tpd	1.7		6.1	ns	VCC = 3.3 V ± 0.3 V	7
Enable time, OE to A or B	ten	1.3		6.9	ns	VCC = 3.3 V ± 0.3 V	7
Disable time, OE to A or B	tdis	2.1		6.9	ns	VCC = 3.3 V ± 0.3 V	7
Enable time, DIR to A or B	ten	1.4		7.2	ns	VCC = 3.3 V ± 0.3 V	7
Disable time, DIR to A or B	tdis	2		7	ns	VCC = 3.3 V ± 0.3 V	7

CAD (KiCad official)

Symbol: SN74LVC16646ADLR
Footprint: Package_SO:SSOP-56_7.5x18.5mm_P0.635mm
3D model: SSOP-56-300mil (KiCad packages3D, STEP)
3D model files: sn74lvc16646adlr-etched.step / sn74lvc16646adlr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); sn74lvc16646adlr.step / sn74lvc16646adlr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Texas Instruments datasheet (18 pp, sha256 79b96a167dc4e0ec, retrieved 2026-10-30, tier: manufacturer)
Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

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SN74LVC16646ADLR

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