component
SN74LVC132APWR
Public Made by Adomby adom
Texas Instruments , TSSOP-14. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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SN74LVC132APWR
Texas Instruments · IC · TSSOP-14
SN74LVC132APWR from Texas Instruments, in a TSSOP-14. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | 1A | input | Channel 1, Input A of the Schmitt-trigger NAND gate (5.5V tolerant input). |
| 2 | 1B | input | Channel 1, Input B of the Schmitt-trigger NAND gate (5.5V tolerant input). |
| 3 | 1Y | output | Channel 1, Output Y of the NAND gate. |
| 4 | 2A | input | Channel 2, Input A of the Schmitt-trigger NAND gate (5.5V tolerant input). |
| 5 | 2B | input | Channel 2, Input B of the Schmitt-trigger NAND gate (5.5V tolerant input). |
| 6 | 2Y | output | Channel 2, Output Y of the NAND gate. |
| 7 | GND | power_in | Ground. |
| 8 | 3Y | output | Channel 3, Output Y of the NAND gate. |
| 9 | 3A | input | Channel 3, Input A of the Schmitt-trigger NAND gate (5.5V tolerant input). |
| 10 | 3B | input | Channel 3, Input B of the Schmitt-trigger NAND gate (5.5V tolerant input). |
| 11 | 4Y | output | Channel 4, Output Y of the NAND gate. |
| 12 | 4A | input | Channel 4, Input A of the Schmitt-trigger NAND gate (5.5V tolerant input). |
| 13 | 4B | input | Channel 4, Input B of the Schmitt-trigger NAND gate (5.5V tolerant input). |
| 14 | VCC | power_in | Positive supply, recommended 1.1V to 3.6V. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | TSSOP-14 |
| Category | |
| Pins | 14 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Supply voltage range | VCC | -0.5 | 6.5 | V | 4 | ||
| Input voltage range | VI | -0.5 | 6.5 | V | 4 | ||
| Input clamp current | IIK | -50 | mA | VI < 0 V | 4 | ||
| Output clamp current | IOK | -50 | mA | VO < 0 V | 4 | ||
| Continuous output current | IO | -50 | 50 | mA | 4 | ||
| Continuous output current through VCC or GND | IO | -100 | 100 | mA | 4 | ||
| Junction temperature | TJ | -65 | 150 | °C | 4 | ||
| Storage temperature | Tstg | -65 | 150 | °C | 4 | ||
| Supply voltage | VCC | 1.1 | 3.6 | V | 4 | ||
| Input voltage | VI | 5.5 | V | 4 | |||
| Input transition rise or fall rate | Δt/Δv | 10 | ns/V | 4 | |||
| Operating free-air temperature | TA | -40 | 125 | °C | 4 | ||
| Junction-to-ambient thermal resistance (PW) | RθJA | 150.8 | °C/W | PW (TSSOP) 14 pins | 5 | ||
| Junction-to-case (top) thermal resistance (PW) | RθJC(top) | 78.3 | °C/W | PW (TSSOP) 14 pins | 5 | ||
| Junction-to-board thermal resistance (PW) | RθJB | 93.8 | °C/W | PW (TSSOP) 14 pins | 5 | ||
| High-level output voltage | VOH | 1.2 | V | IOH= -4mA, VCC=1.65 V | 6 | ||
| High-level output voltage | VOH | 1.75 | V | IOH= -8mA, VCC=2.3 V | 6 | ||
| High-level output voltage | VOH | 2.2 | V | IOH= -12mA, VCC=2.7 V | 6 | ||
| High-level output voltage | VOH | 2.4 | V | IOH= -12mA, VCC=3 V | 6 | ||
| Low-level output voltage | VOL | 0.15 | V | IOH= 100μA, VCC=1.1 V to 3.6 V | 6 | ||
| Low-level output voltage | VOL | 0.2 | V | IOH= 100μA, VCC=1.2 V to 3.6 V | 6 | ||
| Low-level output voltage | VOL | 0.45 | V | IOH= 4mA, VCC=1.65 V | 6 | ||
| Low-level output voltage | VOL | 0.7 | V | IOH= 8mA, VCC=2.3 V | 6 | ||
| Low-level output voltage | VOL | 0.4 | V | IOH= 12mA, VCC=2.7 V | 6 | ||
| Low-level output voltage | VOL | 0.55 | V | IOH= 24mA, VCC=3 V | 6 | ||
| Input leakage current | II | -5 | 5 | µA | VI = VCC or GND, VCC=3.6 V | 6 | |
| Power-off leakage current | Ioff | -10 | 10 | µA | VI or VO = VCC, VCC=0 V | 6 | |
| Supply current | ICC | 40 | µA | VI = VCC or GND, IO = 0, VCC=3.6 V | 6 | ||
| Additional supply current | ΔICC | 500 | µA | One input at VCC - 0.6 V, other inputs at VCC or GND, VCC=2.7 V to 3.6 V | 6 | ||
| Input capacitance | CI | 4.9 | pF | VI = VCC or GND, VCC=3.3 V | 6 | ||
| Output capacitance | CO | 6.3 | pF | VO = VCC or GND, VCC=3.3 V | 6 | ||
| Propagation delay A or B to Y | tpd | 12 | 44 | ns | CL = 15 pF, VCC=1.2 V ± 0.1 V | 6 | |
| Propagation delay A or B to Y | tpd | 9 | 15 | ns | CL = 15 pF, VCC=1.5 V ± 0.12 V | 6 | |
| Positive-going input threshold voltage | VT+ | 0.5 | 0.8 | V | VCC=1.1 V | 5 | |
| Positive-going input threshold voltage | VT+ | 0.53 | 0.9 | V | VCC=1.2 V | 5 | |
| Positive-going input threshold voltage | VT+ | 0.7 | 1.11 | V | VCC=1.5 V | 5 | |
| Positive-going input threshold voltage | VT+ | 0.4 | 1.3 | V | VCC=1.65 V | 5 | |
| Positive-going input threshold voltage | VT+ | 0.6 | 1.5 | V | VCC=1.95 V | 5 | |
| Positive-going input threshold voltage | VT+ | 0.8 | 1.7 | V | VCC=2.3 V | 5 | |
| Positive-going input threshold voltage | VT+ | 0.8 | 2 | V | VCC=2.7 V | 5 | |
| Positive-going input threshold voltage | VT+ | 0.9 | 2 | V | VCC=3 V | 5 | |
| Positive-going input threshold voltage | VT+ | 1.1 | 2 | V | VCC=3.6 V | 5 | |
| Negative-going input threshold voltage | VT- | 0.2 | 0.6 | V | VCC=1.1 V | 5 | |
| Negative-going input threshold voltage | VT- | 0.26 | 0.65 | V | VCC=1.2 V | 5 | |
| Negative-going input threshold voltage | VT- | 0.34 | 0.75 | V | VCC=1.5 V | 5 | |
| Negative-going input threshold voltage | VT- | 0.2 | 0.9 | V | VCC=1.65 V | 5 | |
| Negative-going input threshold voltage | VT- | 0.3 | 1 | V | VCC=1.95 V | 5 | |
| Negative-going input threshold voltage | VT- | 0.4 | 1.2 | V | VCC=2.3 V | 5 | |
| Negative-going input threshold voltage | VT- | 0.4 | 1.4 | V | VCC=2.7 V | 5 | |
| Negative-going input threshold voltage | VT- | 0.6 | 1.5 | V | VCC=3 V | 5 | |
| Negative-going input threshold voltage | VT- | 0.8 | 1.7 | V | VCC=3.6 V | 5 | |
| Hysteresis (VT+ − VT−) | ΔVT | 0.07 | 0.53 | V | VCC=1.1 V | 5 | |
| Hysteresis (VT+ − VT−) | ΔVT | 0.08 | 0.54 | V | VCC=1.2 V | 5 | |
| Hysteresis (VT+ − VT−) | ΔVT | 0.18 | 0.6 | V | VCC=1.5 V | 5 | |
| Hysteresis (VT+ − VT−) | ΔVT | 0.1 | 1.2 | V | VCC=1.65 V | 5 | |
| Hysteresis (VT+ − VT−) | ΔVT | 0.2 | 1.3 | V | VCC=1.95 V | 5 | |
| Hysteresis (VT+ − VT−) | ΔVT | 0.3 | 1.3 | V | VCC=2.3 V | 5 | |
| Hysteresis (VT+ − VT−) | ΔVT | 0.3 | 1.1 | V | VCC=2.7 V | 5 | |
| Hysteresis (VT+ − VT−) | ΔVT | 0.3 | 1.2 | V | VCC=3.6 V | 5 |
CAD (KiCad official)
- Symbol:
SN74LVC132APWR - Footprint:
Package_SO:TSSOP-14_4.4x5mm_P0.65mm - 3D model: TSSOP-14 (KiCad packages3D, STEP)
- 3D model files:
sn74lvc132apwr-etched.step/sn74lvc132apwr-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);sn74lvc132apwr.step/sn74lvc132apwr.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (30 pp, sha256
4fc694fba776be0f, retrieved 2026-10-22, tier: manufacturer) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-sonnet-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# SN74LVC132APWR
**Texas Instruments** · IC · TSSOP-14
SN74LVC132APWR from Texas Instruments, in a TSSOP-14. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | 1A | input | Channel 1, Input A of the Schmitt-trigger NAND gate (5.5V tolerant input). |
| 2 | 1B | input | Channel 1, Input B of the Schmitt-trigger NAND gate (5.5V tolerant input). |
| 3 | 1Y | output | Channel 1, Output Y of the NAND gate. |
| 4 | 2A | input | Channel 2, Input A of the Schmitt-trigger NAND gate (5.5V tolerant input). |
| 5 | 2B | input | Channel 2, Input B of the Schmitt-trigger NAND gate (5.5V tolerant input). |
| 6 | 2Y | output | Channel 2, Output Y of the NAND gate. |
| 7 | GND | power_in | Ground. |
| 8 | 3Y | output | Channel 3, Output Y of the NAND gate. |
| 9 | 3A | input | Channel 3, Input A of the Schmitt-trigger NAND gate (5.5V tolerant input). |
| 10 | 3B | input | Channel 3, Input B of the Schmitt-trigger NAND gate (5.5V tolerant input). |
| 11 | 4Y | output | Channel 4, Output Y of the NAND gate. |
| 12 | 4A | input | Channel 4, Input A of the Schmitt-trigger NAND gate (5.5V tolerant input). |
| 13 | 4B | input | Channel 4, Input B of the Schmitt-trigger NAND gate (5.5V tolerant input). |
| 14 | VCC | power_in | Positive supply, recommended 1.1V to 3.6V. |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | TSSOP-14 |
| Category | |
| Pins | 14 |
## Electrical characteristics
Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Supply voltage range | VCC | -0.5 | | 6.5 | V | | 4 |
| Input voltage range | VI | -0.5 | | 6.5 | V | | 4 |
| Input clamp current | IIK | -50 | | | mA | VI < 0 V | 4 |
| Output clamp current | IOK | -50 | | | mA | VO < 0 V | 4 |
| Continuous output current | IO | -50 | | 50 | mA | | 4 |
| Continuous output current through VCC or GND | IO | -100 | | 100 | mA | | 4 |
| Junction temperature | TJ | -65 | | 150 | °C | | 4 |
| Storage temperature | Tstg | -65 | | 150 | °C | | 4 |
| Supply voltage | VCC | 1.1 | | 3.6 | V | | 4 |
| Input voltage | VI | | | 5.5 | V | | 4 |
| Input transition rise or fall rate | Δt/Δv | | | 10 | ns/V | | 4 |
| Operating free-air temperature | TA | -40 | | 125 | °C | | 4 |
| Junction-to-ambient thermal resistance (PW) | RθJA | | 150.8 | | °C/W | PW (TSSOP) 14 pins | 5 |
| Junction-to-case (top) thermal resistance (PW) | RθJC(top) | | 78.3 | | °C/W | PW (TSSOP) 14 pins | 5 |
| Junction-to-board thermal resistance (PW) | RθJB | | 93.8 | | °C/W | PW (TSSOP) 14 pins | 5 |
| High-level output voltage | VOH | 1.2 | | | V | IOH= -4mA, VCC=1.65 V | 6 |
| High-level output voltage | VOH | 1.75 | | | V | IOH= -8mA, VCC=2.3 V | 6 |
| High-level output voltage | VOH | 2.2 | | | V | IOH= -12mA, VCC=2.7 V | 6 |
| High-level output voltage | VOH | 2.4 | | | V | IOH= -12mA, VCC=3 V | 6 |
| Low-level output voltage | VOL | | | 0.15 | V | IOH= 100μA, VCC=1.1 V to 3.6 V | 6 |
| Low-level output voltage | VOL | | | 0.2 | V | IOH= 100μA, VCC=1.2 V to 3.6 V | 6 |
| Low-level output voltage | VOL | | | 0.45 | V | IOH= 4mA, VCC=1.65 V | 6 |
| Low-level output voltage | VOL | | | 0.7 | V | IOH= 8mA, VCC=2.3 V | 6 |
| Low-level output voltage | VOL | | | 0.4 | V | IOH= 12mA, VCC=2.7 V | 6 |
| Low-level output voltage | VOL | | | 0.55 | V | IOH= 24mA, VCC=3 V | 6 |
| Input leakage current | II | -5 | | 5 | µA | VI = VCC or GND, VCC=3.6 V | 6 |
| Power-off leakage current | Ioff | -10 | | 10 | µA | VI or VO = VCC, VCC=0 V | 6 |
| Supply current | ICC | | | 40 | µA | VI = VCC or GND, IO = 0, VCC=3.6 V | 6 |
| Additional supply current | ΔICC | | | 500 | µA | One input at VCC - 0.6 V, other inputs at VCC or GND, VCC=2.7 V to 3.6 V | 6 |
| Input capacitance | CI | | 4.9 | | pF | VI = VCC or GND, VCC=3.3 V | 6 |
| Output capacitance | CO | | 6.3 | | pF | VO = VCC or GND, VCC=3.3 V | 6 |
| Propagation delay A or B to Y | tpd | 12 | | 44 | ns | CL = 15 pF, VCC=1.2 V ± 0.1 V | 6 |
| Propagation delay A or B to Y | tpd | 9 | | 15 | ns | CL = 15 pF, VCC=1.5 V ± 0.12 V | 6 |
| Positive-going input threshold voltage | VT+ | 0.5 | | 0.8 | V | VCC=1.1 V | 5 |
| Positive-going input threshold voltage | VT+ | 0.53 | | 0.9 | V | VCC=1.2 V | 5 |
| Positive-going input threshold voltage | VT+ | 0.7 | | 1.11 | V | VCC=1.5 V | 5 |
| Positive-going input threshold voltage | VT+ | 0.4 | | 1.3 | V | VCC=1.65 V | 5 |
| Positive-going input threshold voltage | VT+ | 0.6 | | 1.5 | V | VCC=1.95 V | 5 |
| Positive-going input threshold voltage | VT+ | 0.8 | | 1.7 | V | VCC=2.3 V | 5 |
| Positive-going input threshold voltage | VT+ | 0.8 | | 2 | V | VCC=2.7 V | 5 |
| Positive-going input threshold voltage | VT+ | 0.9 | | 2 | V | VCC=3 V | 5 |
| Positive-going input threshold voltage | VT+ | 1.1 | | 2 | V | VCC=3.6 V | 5 |
| Negative-going input threshold voltage | VT- | 0.2 | | 0.6 | V | VCC=1.1 V | 5 |
| Negative-going input threshold voltage | VT- | 0.26 | | 0.65 | V | VCC=1.2 V | 5 |
| Negative-going input threshold voltage | VT- | 0.34 | | 0.75 | V | VCC=1.5 V | 5 |
| Negative-going input threshold voltage | VT- | 0.2 | | 0.9 | V | VCC=1.65 V | 5 |
| Negative-going input threshold voltage | VT- | 0.3 | | 1 | V | VCC=1.95 V | 5 |
| Negative-going input threshold voltage | VT- | 0.4 | | 1.2 | V | VCC=2.3 V | 5 |
| Negative-going input threshold voltage | VT- | 0.4 | | 1.4 | V | VCC=2.7 V | 5 |
| Negative-going input threshold voltage | VT- | 0.6 | | 1.5 | V | VCC=3 V | 5 |
| Negative-going input threshold voltage | VT- | 0.8 | | 1.7 | V | VCC=3.6 V | 5 |
| Hysteresis (VT+ − VT−) | ΔVT | 0.07 | | 0.53 | V | VCC=1.1 V | 5 |
| Hysteresis (VT+ − VT−) | ΔVT | 0.08 | | 0.54 | V | VCC=1.2 V | 5 |
| Hysteresis (VT+ − VT−) | ΔVT | 0.18 | | 0.6 | V | VCC=1.5 V | 5 |
| Hysteresis (VT+ − VT−) | ΔVT | 0.1 | | 1.2 | V | VCC=1.65 V | 5 |
| Hysteresis (VT+ − VT−) | ΔVT | 0.2 | | 1.3 | V | VCC=1.95 V | 5 |
| Hysteresis (VT+ − VT−) | ΔVT | 0.3 | | 1.3 | V | VCC=2.3 V | 5 |
| Hysteresis (VT+ − VT−) | ΔVT | 0.3 | | 1.1 | V | VCC=2.7 V | 5 |
| Hysteresis (VT+ − VT−) | ΔVT | 0.3 | | 1.2 | V | VCC=3.6 V | 5 |
## CAD (KiCad official)
- Symbol: `SN74LVC132APWR`
- Footprint: `Package_SO:TSSOP-14_4.4x5mm_P0.65mm`
- 3D model: TSSOP-14 (KiCad packages3D, STEP)
- 3D model files: `sn74lvc132apwr-etched.step` / `sn74lvc132apwr-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `sn74lvc132apwr.step` / `sn74lvc132apwr.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/lit/ds/symlink/sn74lvc132a.pdf) (30 pp, sha256 `4fc694fba776be0f`, retrieved 2026-10-22, tier: manufacturer)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-sonnet-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/sn74lvc132apwr-datasheet.pdf)