component
SN74LVC126APWR
Public Made by Adomby adom
Texas Instruments Buffers, Drivers, Receivers, Transceivers, TSSOP-14. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownSN74LVC126APWR
Texas Instruments · Buffers, Drivers, Receivers, Transceivers · TSSOP-14
SN74LVC126APWR from Texas Instruments, in a TSSOP-14. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | 1OE | input | Output enable for gate 1; when low, output 1Y is disabled to high impedance, and OE must be tied to GND through a pulldown resistor to ensure high-impedance during power up and power down. |
| 2 | 1A | input | Gate 1 data input; inputs accept up to 5.5 V and must not float, so unused inputs must be tied to VCC or GND. |
| 3 | 1Y | output | Gate 1 3-state buffer output, which is high impedance when 1OE is low; load current must not exceed 25 mA per output. |
| 4 | 2OE | input | Output enable for gate 2; when low, output 2Y is disabled to high impedance, and OE must be tied to GND through a pulldown resistor to ensure high-impedance during power up and power down. |
| 5 | 2A | input | Gate 2 data input; inputs accept up to 5.5 V and must not float, so unused inputs must be tied to VCC or GND. |
| 6 | 2Y | output | Gate 2 3-state buffer output, which is high impedance when 2OE is low; load current must not exceed 25 mA per output. |
| 7 | GND | power_in | Ground pin for the device. |
| 8 | 3Y | output | Gate 3 3-state buffer output, which is high impedance when 3OE is low; load current must not exceed 25 mA per output. |
| 9 | 3A | input | Gate 3 data input; inputs accept up to 5.5 V and must not float, so unused inputs must be tied to VCC or GND. |
| 10 | 3OE | input | Output enable for gate 3; when low, output 3Y is disabled to high impedance, and OE must be tied to GND through a pulldown resistor to ensure high-impedance during power up and power down. |
| 11 | 4Y | output | Gate 4 3-state buffer output, which is high impedance when 4OE is low; load current must not exceed 25 mA per output. |
| 12 | 4A | input | Gate 4 data input; inputs accept up to 5.5 V and must not float, so unused inputs must be tied to VCC or GND. |
| 13 | 4OE | input | Output enable for gate 4; when low, output 4Y is disabled to high impedance, and OE must be tied to GND through a pulldown resistor to ensure high-impedance during power up and power down. |
| 14 | VCC | power_in | Power pin; the device operates from 1.65 V to 3.6 V VCC. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | TSSOP-14 |
| Category | Logic |
| Pins | 14 |
CAD (KiCad official)
- Symbol:
SN74LVC126APWR - Footprint:
Package_SO:TSSOP-14_4.4x5mm_P0.65mm - 3D model: TSSOP-14 (KiCad packages3D, STEP)
- 3D model files:
sn74lvc126apwr-etched.step/sn74lvc126apwr-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);sn74lvc126apwr.step/sn74lvc126apwr.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (36 pp, sha256
b608b8ec6c212e25, retrieved 2026-10-08, tier: manufacturer) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).