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Initial commit: component/sn74lvc10adr

Ray ·a1d7bfad09 ·4d ago
2 files changed +241
README.mdadded+50
@@ -0,0 +1,50 @@+# SN74LVC10ADR++**Texas Instruments** · Logic Gates · SOIC-14++SN74LVC10ADR from Texas Instruments, in a SOIC-14. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.++## Pinout++| Pin | Name | Type | Function |+|---|---|---|---|+| 1 | 1A | input | Input A for 3-input NAND gate channel 1; accepts voltage range 0V to 5.5V |+| 2 | 1B | input | Input B for 3-input NAND gate channel 1; accepts voltage range 0V to 5.5V |+| 3 | 2A | input | Input A for 3-input NAND gate channel 2; accepts voltage range 0V to 5.5V |+| 4 | 2B | input | Input B for 3-input NAND gate channel 2; accepts voltage range 0V to 5.5V |+| 5 | 2C | input | Input C for 3-input NAND gate channel 2; accepts voltage range 0V to 5.5V |+| 6 | 2Y | output | NAND output for gate channel 2; produces logic output voltage range 0V to VCC |+| 7 | GND | power_in | Ground reference for device operation |+| 8 | 3Y | output | NAND output for gate channel 3; produces logic output voltage range 0V to VCC |+| 9 | 3A | input | Input A for 3-input NAND gate channel 3; accepts voltage range 0V to 5.5V |+| 10 | 3B | input | Input B for 3-input NAND gate channel 3; accepts voltage range 0V to 5.5V |+| 11 | 3C | input | Input C for 3-input NAND gate channel 3; accepts voltage range 0V to 5.5V |+| 12 | 1Y | output | NAND output for gate channel 1; produces logic output voltage range 0V to VCC |+| 13 | 1C | input | Input C for 3-input NAND gate channel 1; accepts voltage range 0V to 5.5V |+| 14 | VCC | power_in | Positive supply voltage; recommended operating range 1.65V to 3.6V |++## Key specifications++| Parameter | Value |+|---|---|+| Manufacturer | Texas Instruments |+| Package | SOIC-14 |+| Category | Logic |+| Pins | 14 |++## CAD (KiCad official)++- Symbol: `SN74LVC10ADR`+- Footprint: `Package_SO:SOIC-14_3.9x8.7mm_P1.27mm`+- 3D model: SOIC-14 (KiCad packages3D, STEP)+- 3D model files: `sn74lvc10adr-etched.step` / `sn74lvc10adr-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `sn74lvc10adr.step` / `sn74lvc10adr.glb` are the bare package body.++## Provenance++Data extracted from the manufacturer datasheet, not a distributor listing:++- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/lit/ds/symlink/sn74lvc10a.pdf) (32 pp, sha256 `ffbed261dcf61c42`, retrieved 2026-10-01, tier: manufacturer)+- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-4-5-20251001` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.+- **CAD:** KiCad official libraries (CC-BY-SA 4.0).++[Datasheet PDF](docs/sn74lvc10adr-datasheet.pdf)
page.jsonadded+191
@@ -0,0 +1,191 @@+{+  "slug": "sn74lvc10adr",+  "version": "0.1.0",+  "type": "component",+  "description": "Texas Instruments Logic Gates, SOIC-14. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.",+  "tags": [+    "component",+    "logic",+    "sn74lvc10adr",+    "factory-2.0.0",+    "extractor-text"+  ],+  "dependencies": {},+  "hero": {+    "type": "image",+    "path": "docs/hero.png"+  },+  "files": [+    "page.json",+    "README.md",+    "sn74lvc10adr.kicad_sym",+    "sn74lvc10adr.kicad_mod",+    "sn74lvc10adr.glb",+    "sn74lvc10adr.step",+    "sn74lvc10adr.lbr",+    "docs/hero.png",+    "docs/sn74lvc10adr-datasheet.pdf",+    "viewers/symbol.html",+    "viewers/footprint.html"+  ],+  "component": {+    "mpn": "SN74LVC10ADR",+    "manufacturer": "Texas Instruments",+    "package": "SOIC-14",+    "pin_count": 14,+    "category": "Logic",+    "subcategory": "Logic Gates",+    "datasheet": "https://www.ti.com/lit/ds/symlink/sn74lvc10a.pdf",+    "parts": {+      "symbol": "sn74lvc10adr.kicad_sym",+      "footprint": "sn74lvc10adr.kicad_mod",+      "model_3d": "sn74lvc10adr-etched.glb",+      "model_3d_plain": "sn74lvc10adr.glb",+      "model_3d_step": "sn74lvc10adr-etched.step",+      "model_3d_step_plain": "sn74lvc10adr.step",+      "lbr": "sn74lvc10adr.lbr"+    },+    "distributor_links": {+      "lcsc": "C2878730",+      "digikey": "296-38252-2-ND",+      "mouser": "595-SN74LVC10ADR"+    },+    "distributor_check": {+      "checked_at": "2026-10-01T15:26:25Z",+      "source": "Component Ocean /api/assign-pns",+      "digikey": {+        "pn": "296-38252-2-ND",+        "status": "found"+      },+      "mouser": {+        "pn": "595-SN74LVC10ADR",+        "status": "found"+      }+    },+    "pins": [+      {+        "number": "1",+        "name": "1A",+        "type": "input",+        "description": "Input A for 3-input NAND gate channel 1; accepts voltage range 0V to 5.5V"+      },+      {+        "number": "2",+        "name": "1B",+        "type": "input",+        "description": "Input B for 3-input NAND gate channel 1; accepts voltage range 0V to 5.5V"+      },+      {+        "number": "3",+        "name": "2A",+        "type": "input",+        "description": "Input A for 3-input NAND gate channel 2; accepts voltage range 0V to 5.5V"+      },+      {+        "number": "4",+        "name": "2B",+        "type": "input",+        "description": "Input B for 3-input NAND gate channel 2; accepts voltage range 0V to 5.5V"+      },+      {+        "number": "5",+        "name": "2C",+        "type": "input",+        "description": "Input C for 3-input NAND gate channel 2; accepts voltage range 0V to 5.5V"+      },+      {+        "number": "6",+        "name": "2Y",+        "type": "output",+        "description": "NAND output for gate channel 2; produces logic output voltage range 0V to VCC"+      },+      {+        "number": "7",+        "name": "GND",+        "type": "power_in",+        "description": "Ground reference for device operation"+      },+      {+        "number": "8",+        "name": "3Y",+        "type": "output",+        "description": "NAND output for gate channel 3; produces logic output voltage range 0V to VCC"+      },+      {+        "number": "9",+        "name": "3A",+        "type": "input",+        "description": "Input A for 3-input NAND gate channel 3; accepts voltage range 0V to 5.5V"+      },+      {+        "number": "10",+        "name": "3B",+        "type": "input",+        "description": "Input B for 3-input NAND gate channel 3; accepts voltage range 0V to 5.5V"+      },+      {+        "number": "11",+        "name": "3C",+        "type": "input",+        "description": "Input C for 3-input NAND gate channel 3; accepts voltage range 0V to 5.5V"+      },+      {+        "number": "12",+        "name": "1Y",+        "type": "output",+        "description": "NAND output for gate channel 1; produces logic output voltage range 0V to VCC"+      },+      {+        "number": "13",+        "name": "1C",+        "type": "input",+        "description": "Input C for 3-input NAND gate channel 1; accepts voltage range 0V to 5.5V"+      },+      {+        "number": "14",+        "name": "VCC",+        "type": "power_in",+        "description": "Positive supply voltage; recommended operating range 1.65V to 3.6V"+      }+    ],+    "provenance": {+      "extractor": "extract_pins 0.3",+      "factory_chain": {+        "factory": "2.0.0",+        "extractor": "extract_pins 0.3",+        "primary_model": "claude-haiku-4-5-20251001",+        "primary_mode": "text",+        "consensus_model": "claude-sonnet-5-5",+        "consensus": "agreed",+        "guards": "pin_guards 0.1: passed",+        "guard_notes": [],+        "pages_sent": 32,+        "cost_usd": 0.142,+        "at": "2026-10-01T15:26:09"+      },+      "datasheet": {+        "url": "https://www.ti.com/lit/ds/symlink/sn74lvc10a.pdf",+        "pages": 32,+        "sha256": "ffbed261dcf61c42",+        "source_tier": "mfr"+      },+      "cad": "KiCad official (CC-BY-SA 4.0)",+      "pins": {+        "total": 14,+        "described": 14,+        "cites_pages": true,+        "refuses_to_fabricate": true+      }+    },+    "viewers": {+      "symbol": "viewers/symbol.html",+      "footprint": "viewers/footprint.html"+    }+  },+  "visibility": "public",+  "org": "adom",+  "author": {+    "name": "Ray",+    "email": "[email protected]"+  }+}\ No newline at end of file