# SN74LVC00AQDREP

**Texas Instruments** · Logic ICs · SOIC-14

SN74LVC00AQDREP from Texas Instruments, in a SOIC-14. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | 1A | input | Input of gate 1; the datasheet states inputs accept voltages up to 5.5 V. |
| 2 | 1B | input | Input of gate 1; the datasheet states inputs accept voltages up to 5.5 V. |
| 3 | 1Y | output | Output of gate 1 (Y = A NAND B); output voltage range is 0 to VCC. |
| 4 | 2A | input | Input of gate 2; the datasheet states inputs accept voltages up to 5.5 V. |
| 5 | 2B | input | Input of gate 2; the datasheet states inputs accept voltages up to 5.5 V. |
| 6 | 2Y | output | Output of gate 2 (Y = A NAND B); output voltage range is 0 to VCC. |
| 7 | GND | power_in | Ground reference pin for the device. |
| 8 | 3Y | output | Output of gate 3 (Y = A NAND B); output voltage range is 0 to VCC. |
| 9 | 3A | input | Input of gate 3; the datasheet states inputs accept voltages up to 5.5 V. |
| 10 | 3B | input | Input of gate 3; the datasheet states inputs accept voltages up to 5.5 V. |
| 11 | 4Y | output | Output of gate 4 (Y = A NAND B); output voltage range is 0 to VCC. |
| 12 | 4A | input | Input of gate 4; the datasheet states inputs accept voltages up to 5.5 V. |
| 13 | 4B | input | Input of gate 4; the datasheet states inputs accept voltages up to 5.5 V. |
| 14 | VCC | power_in | Supply pin; recommended operating supply range is 2 V to 3.6 V. |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | SOIC-14 |
| Category | Logic ICs |
| Pins | 14 |

## Electrical characteristics

Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).

| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Supply voltage range | VCC | -0.5 |  | 6.5 | V |  | 2 |
| Input voltage range | VI | -0.5 |  | 6.5 | V |  | 2 |
| Input clamp current | IIK | -50 |  |  | mA | VI < 0 V | 2 |
| Output clamp current | IOK | -50 |  |  | mA | VO < 0 V | 2 |
| Continuous output current | IO | -50 |  | 50 | mA |  | 2 |
| Continuous current through VCC or GND |  | -100 |  | 100 | mA |  | 2 |
| Storage temperature range | Tstg | -65 |  | 150 | °C |  | 2 |
| Package thermal impedance, D package | θJA |  | 86 |  | °C/W | D package | 2 |
| Package thermal impedance, PW package | θJA |  | 113 |  | °C/W | PW package | 2 |
| Operating supply voltage | VCC | 2 |  | 3.6 | V | Operating | 2 |
| Data retention supply voltage | VCC | 1.5 |  |  | V | Data retention only | 2 |
| High-level input voltage | VIH | 2 |  |  | V | VCC = 2.7 V to 3.6 V | 2 |
| Low-level input voltage | VIL |  |  | 0.8 | V | VCC = 2.7 V to 3.6 V | 2 |
| Input voltage | VI | 0 |  | 5.5 | V |  | 2 |
| Output voltage | VO | 0 |  |  | V | upper limit VCC | 2 |
| High-level output current | IOH | -12 |  |  | mA | VCC = 2.7 V | 2 |
| High-level output current | IOH | -24 |  |  | mA | VCC = 3 V | 2 |
| Low-level output current | IOL |  |  | 12 | mA | VCC = 2.7 V | 2 |
| Low-level output current | IOL |  |  | 24 | mA | VCC = 3 V | 2 |
| Operating free-air temperature, Q suffix | TA | -40 |  | 125 | °C | Q suffix | 2 |
| High-level output voltage | VOH | 2.2 |  |  | V | IOH = -12 mA, VCC = 2.7 V | 3 |
| High-level output voltage | VOH | 2.4 |  |  | V | IOH = -12 mA, VCC = 3 V | 3 |
| Low-level output voltage | VOL |  |  | 0.2 | V | IOL = 100 µA, VCC = 2.7 V to 3.6 V | 3 |
| Low-level output voltage | VOL |  |  | 0.4 | V | IOL = 12 mA, VCC = 2.7 V | 3 |
| Low-level output voltage | VOL |  |  | 0.55 | V | IOL = 24 mA, VCC = 3 V | 3 |
| Input current | II | -5 |  | 5 | µA | VI = 5.5 V or GND, VCC = 3.6 V | 3 |
| Quiescent supply current | ICC |  |  | 10 | µA | VI = VCC or GND, IO = 0, VCC = 3.6 V | 3 |
| Additional quiescent supply current per input | ∆ICC |  |  | 500 | µA | One input at VCC - 0.6 V, other inputs at VCC or GND, VCC = 2.7 V to 3.6 V | 3 |
| Input capacitance | Ci |  | 5 |  | pF | VI = VCC or GND, VCC = 3.3 V | 3 |
| Propagation delay A or B to Y | tpd | 1 |  | 5.1 | ns | VCC = 2.7 V, see Figure 1 | 3 |
| Propagation delay A or B to Y | tpd | 1 |  | 4.3 | ns | VCC = 3.3 V ± 0.3 V, see Figure 1 | 3 |
| Power dissipation capacitance per gate | Cpd |  | 18 |  | pF | f = 10 MHz, VCC = 2.5 V | 3 |
| Power dissipation capacitance per gate | Cpd |  | 19 |  | pF | f = 10 MHz, VCC = 3.3 V | 3 |

## CAD (KiCad official)

- Symbol: `SN74LVC00AQDREP`
- Footprint: `Package_SO:SOIC-14_3.9x8.7mm_P1.27mm`
- 3D model: SOIC-14 (KiCad packages3D, STEP)
- 3D model files: `sn74lvc00aqdrep-etched.step` / `sn74lvc00aqdrep-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `sn74lvc00aqdrep.step` / `sn74lvc00aqdrep.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/lit/ds/symlink/sn74lvc00aqdrep.pdf) (12 pp, sha256 `212b9089ed9af8e3`, retrieved 2026-10-27, tier: manufacturer)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/sn74lvc00aqdrep-datasheet.pdf)