component

SN74LV8151DWR

Public Made by Adom

by adom

Texas Instruments Buffer/Driver/Transceiver, SOIC-24-300mil. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentlogic icssn74lv8151dwrfactory-2.0.0extractor-text

Verified SN74LV8151DWR

by Ray · last 31 Oct 2026 · 1 record · files match
SymbolFootprint3D modelPins

Verification log 1 record

31 Oct 2026RayPublished by the parts factory: tier mfr, 24 pinsfiles match
SymbolFootprint3D modelPinsfor all variants
  • ✓component-page-verify: PASS
  • ✓cad_props: Datasheet, MPN and distributor properties match page.json
  • ✓component: SN74LV8151DWR · SOIC-24-300mil · 24 pins
  • ✓copper: 24 copper pads, none touching another net
  • ✓datasheet: all 24 pin names found in the 20-page datasheet
  • ✓distributor: lcsc C2859850, digikey 296-18749-2-ND, mouser 595-SN74LV8151DWR
  • ✓family: SOIC-24W_7.5x15.4mm_P1.27mm
  • ✓files: 7 declared files present
  • ✓hero: docs/hero.png 4000x2500
  • ✓lbr: OK: /tmp/cpv-9kdxxpia/x.lbr is a valid EAGLE .lbr with complete deviceset
  • ✓license: CC-BY-SA-4.0
  • ✓models_3d: 2 records
  • •package_fit (skip): the datasheet dimensions give no height or body size to compare
  • ✓pads: 24 pins = 24 pads
  • ✓pose: 2 STEP(s) Z-up, seated, centred
  • ✓symbol: 24 pins agree
  • ✓visibility: public, source open
Evidencedatasheet
Verified files✓ sn74lv8151dwr.kicad_sym✓ sn74lv8151dwr.kicad_mod✓ sn74lv8151dwr.step
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Generated by kicad-footprint-generator · KiCad file format 20260206
Name Last commit message Last updated
docs Publish 0.1.0 · Ray 12h ago
viewers sn74lv8151dwr: viewers · Ray 12h ago
package.json Publish 0.1.0 · Ray 12h ago
page.json Set visibility: public · Ray 12h ago
README.md Publish 0.1.0 · Ray 12h ago
sn74lv8151dwr-etched.glb Publish 0.1.0 · Ray 12h ago
sn74lv8151dwr-etched.step sn74lv8151dwr: factory component page (tier=mfr) · Ray 12h ago
sn74lv8151dwr-hero.glb sn74lv8151dwr: hero GLB from the etched model (keeps the MPN mark) · Ray 12h ago
sn74lv8151dwr-hero.overlay.json Publish 0.1.0 · Ray 12h ago
sn74lv8151dwr.glb Publish 0.1.0 · Ray 12h ago
sn74lv8151dwr.kicad_mod Publish 0.1.0 · Ray 12h ago
sn74lv8151dwr.kicad_sym Publish 0.1.0 · Ray 12h ago
sn74lv8151dwr.lbr Publish 0.1.0 · Ray 12h ago
sn74lv8151dwr.step Publish 0.1.0 · Ray 12h ago
verification.json Verified: Published by the parts factory: tier mfr, 24 pins · Ray 12h ago

SN74LV8151DWR

Texas Instruments · Buffer/Driver/Transceiver · SOIC-24-300mil

SN74LV8151DWR from Texas Instruments, in a SOIC-24-300mil. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 T/C input Polarity control: high gives noninverted (true) Y outputs, low gives inverted (complementary) Y outputs; unused inputs must be held at VCC or GND.
2 A input Schmitt-trigger buffer input that drives output P.
3 B input Schmitt-trigger inverter input that drives output N.
4 D1 input Schmitt-trigger data input for channel 1, passed to Y1 when OE is low.
5 D2 input Schmitt-trigger data input for channel 2, passed to Y2 when OE is low.
6 D3 input Schmitt-trigger data input for channel 3, passed to Y3 when OE is low.
7 D4 input Schmitt-trigger data input for channel 4, passed to Y4 when OE is low.
8 D5 input Schmitt-trigger data input for channel 5, passed to Y5 when OE is low.
9 D6 input Schmitt-trigger data input for channel 6, passed to Y6 when OE is low.
10 D7 input Schmitt-trigger data input for channel 7, passed to Y7 when OE is low.
11 D8 input Schmitt-trigger data input for channel 8, passed to Y8 when OE is low.
12 GND power_in Ground pin.
13 OE input Active-low output enable: low passes Dn to Yn, high puts Y outputs in high-impedance; tie to VCC through a pullup resistor for power up/down.
14 Y8 tri_state 3-state output for channel 8, true or complementary of D8 depending on T/C.
15 Y7 tri_state 3-state output for channel 7, true or complementary of D7 depending on T/C.
16 Y6 tri_state 3-state output for channel 6, true or complementary of D6 depending on T/C.
17 Y5 tri_state 3-state output for channel 5, true or complementary of D5 depending on T/C.
18 Y4 tri_state 3-state output for channel 4, true or complementary of D4 depending on T/C.
19 Y3 tri_state 3-state output for channel 3, true or complementary of D3 depending on T/C.
20 Y2 tri_state 3-state output for channel 2, true or complementary of D2 depending on T/C.
21 Y1 tri_state 3-state output for channel 1, true or complementary of D1 depending on T/C.
22 N output Output of the Schmitt-trigger inverter path from B.
23 P output Output of the Schmitt-trigger buffer path from A.
24 VCC power_in Supply voltage, 2 V to 5.5 V recommended operating range.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package SOIC-24-300mil
Category Logic ICs
Pins 24

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Supply voltage VCC VCC 2 5.5 V 4
High-level input voltage (2 V) VIH 1.5 V VCC = 2 V 4
Low-level input voltage (2 V) VIL 0.5 V VCC = 2 V 4
Input voltage VI 0 5.5 V 4
Output voltage, 3-state VO 0 5.5 V 3-state 4
Output voltage, high or low state VO 0 V High or low state 4
High-level output current (2 V) IOH -50 µA VCC = 2 V 4
High-level output current (2.3 V to 2.7 V) IOH -2 mA VCC = 2.3 V to 2.7 V 4
High-level output current (3 V to 3.6 V) IOH -6 mA VCC = 3 V to 3.6 V 4
High-level output current (4.5 V to 5.5 V) IOH -12 mA VCC = 4.5 V to 5.5 V 4
Low-level output current (2 V) IOL 50 µA VCC = 2 V 4
Low-level output current (2.3 V to 2.7 V) IOL 2 mA VCC = 2.3 V to 2.7 V 4
Low-level output current (3 V to 3.6 V) IOL 6 mA VCC = 3 V to 3.6 V 4
Low-level output current (4.5 V to 5.5 V) IOL 12 mA VCC = 4.5 V to 5.5 V 4
Input transition rise or fall rate, T/C and OE inputs (2.3 V to 2.7 V) ∆t/∆v 200 ns/V T/C, OE inputs; VCC = 2.3 V to 2.7 V 4
Input transition rise or fall rate, T/C and OE inputs (3 V to 3.6 V) ∆t/∆v 100 ns/V T/C, OE inputs; VCC = 3 V to 3.6 V 4
Input transition rise or fall rate, T/C and OE inputs (4.5 V to 5.5 V) ∆t/∆v 20 ns/V T/C, OE inputs; VCC = 4.5 V to 5.5 V 4
Input transition rise or fall rate, A, B, D inputs (2.3 V to 2.7 V) ∆t/∆v 4 ms/V A, B, D inputs; VCC = 2.3 V to 2.7 V 4
Input transition rise or fall rate, A, B, D inputs (3 V to 3.6 V) ∆t/∆v 3 ms/V A, B, D inputs; VCC = 3 V to 3.6 V 4
Input transition rise or fall rate, A, B, D inputs (4.5 V to 5.5 V) ∆t/∆v 2 ms/V A, B, D inputs; VCC = 4.5 V to 5.5 V 4
Operating free-air temperature TA -40 85 °C 4
Supply voltage range VCC -0.5 7 V 3
Input voltage range VI -0.5 7 V 3
Voltage applied to any output in high-impedance or power-off state VO -0.5 7 V 3
Output voltage range VO -0.5 V 3
Input clamp current IIK -20 mA VI < 0 3
Output clamp current IOK -50 mA VO < 0 3
Continuous output current IO -35 35 mA VO = 0 to VCC 3
Continuous current through VCC or GND -70 70 mA 3
Storage temperature range Tstg -65 150 °C 3
High-level output voltage (2.3 V) VOH 2 V IOH = −2 mA; VCC = 2.3 V 5
High-level output voltage (3 V) VOH 2.48 V IOH = −6 mA; VCC = 3 V 5
High-level output voltage (4.5 V) VOH 3.8 V IOH = −12 mA; VCC = 4.5 V 5
Low-level output voltage (2 V to 5.5 V) VOL 0.1 V IOL = 50 µA; VCC = 2 V to 5.5 V 5
Low-level output voltage (2.3 V) VOL 0.4 V IOL = 2 mA; VCC = 2.3 V 5
Low-level output voltage (3 V) VOL 0.44 V IOL = 6 mA; VCC = 3 V 5
Low-level output voltage (4.5 V) VOL 0.55 V IOL = 12 mA; VCC = 4.5 V 5
Input current II -1 1 µA VI = 5.5 V or GND; VCC = 0 to 5.5 V 5
Off-state output current IOZ -5 5 µA VO = VCC or GND; VCC = 5.5 V 5
Supply current ICC 20 µA VI = VCC or GND, IO = 0; VCC = 5.5 V 5
Power-off leakage current Ioff 5 µA VI or VO = 0 to 5.5 V; VCC = 0 5
Hysteresis (2.5 V) ∆VT 0.25 1 V A, B, and D inputs; VCC = 2.5 V 5
Hysteresis (3.3 V) ∆VT 0.33 1.32 V A, B, and D inputs; VCC = 3.3 V 5
Hysteresis (5 V) ∆VT 0.5 2 V A, B, and D inputs; VCC = 5 V 5
Propagation delay A or B to P or N tpd 1 9 15 ns VCC = 5 V ± 0.5 V; CL = 15 pF 6
Propagation delay D to Y tpd 1 10 16 ns VCC = 5 V ± 0.5 V; CL = 15 pF 6
Propagation delay T/C to Y tpd 1 11 17 ns VCC = 5 V ± 0.5 V; CL = 15 pF 6
Enable time OE to Y ten 1 6 10.5 ns VCC = 5 V ± 0.5 V; CL = 15 pF 6
Disable time OE to Y tdis 1 6 10 ns VCC = 5 V ± 0.5 V; CL = 15 pF 6
Propagation delay A or B to P or N tpd 1 11 18 ns VCC = 5 V ± 0.5 V; CL = 50 pF 6
Propagation delay D to Y tpd 1 12 20 ns VCC = 5 V ± 0.5 V; CL = 50 pF 6
Propagation delay T/C to Y tpd 1 13 21 ns VCC = 5 V ± 0.5 V; CL = 50 pF 6
Enable time OE to Y ten 1 8 12.5 ns VCC = 5 V ± 0.5 V; CL = 50 pF 6
Disable time OE to Y tdis 1 8 11.5 ns VCC = 5 V ± 0.5 V; CL = 50 pF 6
Propagation delay A or B to P or N tpd 1 14 26 ns VCC = 3.3 V ± 0.3 V; CL = 15 pF 6
Propagation delay D to Y tpd 1 15 29 ns VCC = 3.3 V ± 0.3 V; CL = 15 pF 6
Propagation delay T/C to Y tpd 1 16 30 ns VCC = 3.3 V ± 0.3 V; CL = 15 pF 6
Enable time OE to Y ten 1 9 16 ns VCC = 3.3 V ± 0.3 V; CL = 15 pF 6
Disable time OE to Y tdis 1 8 14 ns VCC = 3.3 V ± 0.3 V; CL = 15 pF 6
Propagation delay A or B to P or N tpd 1 22 45 ns VCC = 2.5 V ± 0.2 V; CL = 15 pF 5

CAD (KiCad official)

  • Symbol: SN74LV8151DWR
  • Footprint: Package_SO:SOIC-24W_7.5x15.4mm_P1.27mm
  • 3D model: SOIC-24-300mil (KiCad packages3D, STEP)
  • 3D model files: sn74lv8151dwr-etched.step / sn74lv8151dwr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); sn74lv8151dwr.step / sn74lv8151dwr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (20 pp, sha256 d300a8735c5a928d, retrieved 2026-10-31, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text+vision), consensus claude-opus-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF