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SN74LV74APWR

Public Made by Adom

by adom

Texas Instruments Flip Flops, TSSOP-14. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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SN74LV74APWR

Texas Instruments · Flip Flops · TSSOP-14

SN74LV74APWR from Texas Instruments, in a TSSOP-14. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 1CLR input Clear input for flip-flop 1.
2 1D input Data input for flip-flop 1.
3 1CLK input Clock input for flip-flop 1.
4 1PRE input Preset input for flip-flop 1.
5 1Q output Output 1Q of flip-flop 1.
6 1Q output Complementary output 1Q of flip-flop 1.
7 GND power_in Ground reference.
8 2Q output Complementary output 2Q of flip-flop 2.
9 2Q output Output 2Q of flip-flop 2.
10 2PRE input Preset input for flip-flop 2.
11 2CLK input Clock input for flip-flop 2.
12 2D input Data input for flip-flop 2.
13 2CLR input Clear input for flip-flop 2.
14 VCC power_in Supply voltage input.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package TSSOP-14
Category Logic
Pins 14

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Supply voltage VCC -0.5 7 V 4
Input voltage VI -0.5 7 V 4
Voltage applied to any output in high-impedance or power-off state VO -0.5 7 V 4
Input clamp current IIK -20 mA VI < 0 4
Output clamp current IOK -50 mA VO < 0 4
Continuous output current IO -25 25 mA VO = 0 to VCC 4
Continuous current through VCC or GND -50 50 mA 4
Package thermal impedance, PW package θJA 113 °C/W PW package, per JESD 51-7 4
Storage temperature Tstg -65 150 °C 4
Supply voltage VCC 2 5.5 V SN74LV74A 5
Input voltage VI 0 5.5 V 5
High-level output current IOH -50 µA VCC = 2 V 5
High-level output current IOH -2 mA VCC = 2.3 V to 2.7 V 5
High-level output current IOH -6 mA VCC = 3 V to 3.6 V 5
High-level output current IOH -12 mA VCC = 4.5 V to 5.5 V 5
Low-level output current IOL 50 µA VCC = 2 V 5
Low-level output current IOL 2 mA VCC = 2.3 V to 2.7 V 5
Low-level output current IOL 6 mA VCC = 3 V to 3.6 V 5
Low-level output current IOL 12 mA VCC = 4.5 V to 5.5 V 5
Input transition rise or fall rate Δt/Δv 200 ns/V VCC = 2.3 V to 2.7 V 5
Input transition rise or fall rate Δt/Δv 100 ns/V VCC = 3 V to 3.6 V 5
Input transition rise or fall rate Δt/Δv 20 ns/V VCC = 4.5 V to 5.5 V 5
Operating free-air temperature TA -40 125 °C SN74LV74A 5
High-level output voltage VOH 2 V IOH = -2 mA, VCC = 2.3 V, TA = -40°C to 85°C 5
High-level output voltage VOH 2.48 V IOH = -6 mA, VCC = 3 V, TA = -40°C to 85°C 5
High-level output voltage VOH 3.8 V IOH = -12 mA, VCC = 4.5 V, TA = -40°C to 85°C 5
Low-level output voltage VOL 0.1 V IOL = 50 µA, VCC = 2 V to 5.5 V, TA = -40°C to 85°C 5
Low-level output voltage VOL 0.4 V IOL = 2 mA, VCC = 2.3 V, TA = -40°C to 85°C 5
Low-level output voltage VOL 0.44 V IOL = 6 mA, VCC = 3 V, TA = -40°C to 85°C 5
Low-level output voltage VOL 0.55 V IOL = 12 mA, VCC = 4.5 V, TA = -40°C to 85°C 5
Input leakage current II -1 1 µA VI = 5.5 V or GND, VCC = 0 to 5.5 V 5
Quiescent supply current ICC 20 µA VI = VCC or GND, IO = 0, VCC = 5.5 V 5
Power-off leakage current Ioff 5 µA VI or VO = 5.5 V, VCC = 0 5
Input capacitance Ci 2 pF VI = VCC or GND, VCC = 3.3 V 5
Pulse duration, PRE or CLR low tw 8 ns VCC = 2.5 V ± 0.2 V, TA = -40°C to 85°C 6
Pulse duration, CLK tw 8 ns VCC = 2.5 V ± 0.2 V, TA = -40°C to 85°C 6
Setup time before CLK↑, data tsu 8 ns VCC = 2.5 V ± 0.2 V, TA = -40°C to 85°C 6
Setup time before CLK↑, PRE or CLR inactive tsu 7 ns VCC = 2.5 V ± 0.2 V, TA = -40°C to 85°C 6
Hold time, data after CLK↑ th 0.5 ns VCC = 2.5 V ± 0.2 V, TA = -40°C to 85°C 6
Pulse duration, PRE or CLR low tw 6 ns VCC = 3.3 V ± 0.3 V, TA = -40°C to 85°C 7
Pulse duration, CLK tw 6 ns VCC = 3.3 V ± 0.3 V, TA = -40°C to 85°C 7
Setup time before CLK↑, data tsu 6 ns VCC = 3.3 V ± 0.3 V, TA = -40°C to 85°C 7
Setup time before CLK↑, PRE or CLR inactive tsu 5 ns VCC = 3.3 V ± 0.3 V, TA = -40°C to 85°C 7
Hold time, data after CLK↑ th 0.5 ns VCC = 3.3 V ± 0.3 V, TA = -40°C to 85°C 7
Pulse duration, PRE or CLR low tw 5 ns VCC = 5 V ± 0.5 V, TA = -40°C to 85°C 7
Pulse duration, CLK tw 5 ns VCC = 5 V ± 0.5 V, TA = -40°C to 85°C 7
Setup time before CLK↑, data tsu 5 ns VCC = 5 V ± 0.5 V, TA = -40°C to 85°C 7
Setup time before CLK↑, PRE or CLR inactive tsu 3 ns VCC = 5 V ± 0.5 V, TA = -40°C to 85°C 7

CAD (KiCad official)

  • Symbol: SN74LV74APWR
  • Footprint: Package_SO:TSSOP-14_4.4x5mm_P0.65mm
  • 3D model: TSSOP-14 (KiCad packages3D, STEP)
  • 3D model files: sn74lv74apwr-etched.step / sn74lv74apwr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); sn74lv74apwr.step / sn74lv74apwr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (32 pp, sha256 73d4fdf490519f25, retrieved 2026-10-17, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF