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Ray sn74lv595apwr: white body in tscircuit (pre-1.8 etch structure under an assembly instance); Ray 2026-10-19: black IC bo… 62ab503
{
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  "type": "component",
  "slug": "sn74lv595apwr",
  "title": "SN74LV595APWR",
  "brief": "Texas Instruments Shifting Register, TSSOP-16. Pinout extracted from the datasheet, KiCad symbol/footprint/3D.",
  "version": "0.2.0",
  "license": "CC-BY-SA-4.0",
  "tags": [
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  "component": {
    "mpn": "SN74LV595APWR",
    "manufacturer": "Texas Instruments",
    "package": "TSSOP-16",
    "pin_count": 16,
    "category": "Logic",
    "subcategory": "Shifting Register",
    "datasheet": "https://www.ti.com/lit/ds/symlink/sn74lv595a.pdf",
    "parts": {
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      "footprint": "sn74lv595apwr.kicad_mod",
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      "model_3d_plain": "sn74lv595apwr.glb",
      "model_3d_step": "sn74lv595apwr-etched.step",
      "model_3d_step_plain": "sn74lv595apwr.step",
      "lbr": "sn74lv595apwr.lbr"
    },
    "distributor_links": {
      "digikey": "296-3843-2-ND",
      "mouser": "595-SN74LV595APWR",
      "lcsc": "C116847"
    },
    "pins": [
      {
        "number": "1",
        "name": "QB",
        "type": "tri_state",
        "description": "Parallel output B from the 8-bit storage register. 3-state CMOS output; disabled to high-impedance when OE is HIGH."
      },
      {
        "number": "2",
        "name": "QC",
        "type": "tri_state",
        "description": "Parallel output C from the 8-bit storage register. 3-state CMOS output; disabled to high-impedance when OE is HIGH."
      },
      {
        "number": "3",
        "name": "QD",
        "type": "tri_state",
        "description": "Parallel output D from the 8-bit storage register. 3-state CMOS output; disabled to high-impedance when OE is HIGH."
      },
      {
        "number": "4",
        "name": "QE",
        "type": "tri_state",
        "description": "Parallel output E from the 8-bit storage register. 3-state CMOS output; disabled to high-impedance when OE is HIGH."
      },
      {
        "number": "5",
        "name": "QF",
        "type": "tri_state",
        "description": "Parallel output F from the 8-bit storage register. 3-state CMOS output; disabled to high-impedance when OE is HIGH."
      },
      {
        "number": "6",
        "name": "QG",
        "type": "tri_state",
        "description": "Parallel output G from the 8-bit storage register. 3-state CMOS output; disabled to high-impedance when OE is HIGH."
      },
      {
        "number": "7",
        "name": "QH",
        "type": "tri_state",
        "description": "Parallel output H from the 8-bit storage register. 3-state CMOS output; disabled to high-impedance when OE is HIGH."
      },
      {
        "number": "8",
        "name": "GND",
        "type": "power_in",
        "description": "Ground reference (0 V). All signal voltages are referenced to this pin."
      },
      {
        "number": "9",
        "name": "QH'",
        "type": "output",
        "description": "Serial data output from the shift register's last stage (QH of the shift register, before the storage register). Used to cascade multiple '595A devices; not 3-state."
      },
      {
        "number": "10",
        "name": "SRCLR",
        "type": "input",
        "description": "Shift register direct clear input, active LOW. When LOW, asynchronously clears the 8-bit shift register."
      },
      {
        "number": "11",
        "name": "SRCLK",
        "type": "input",
        "description": "Shift register clock input. Positive-edge triggered; on each rising edge the SER data is shifted into the 8-bit shift register."
      },
      {
        "number": "12",
        "name": "RCLK",
        "type": "input",
        "description": "Storage register clock input. Positive-edge triggered; on each rising edge the shift register contents are latched into the 8-bit storage (D-type) register that drives QA..QH."
      },
      {
        "number": "13",
        "name": "OE",
        "type": "input",
        "description": "Output enable, active LOW. When LOW the parallel outputs QA..QH are enabled; when HIGH the outputs go to high impedance (3-state)."
      },
      {
        "number": "14",
        "name": "SER",
        "type": "input",
        "description": "Serial data input to the 8-bit shift register. Sampled on the rising edge of SRCLK."
      },
      {
        "number": "15",
        "name": "QA",
        "type": "tri_state",
        "description": "Parallel output A from the 8-bit storage register. 3-state CMOS output; disabled to high-impedance when OE is HIGH."
      },
      {
        "number": "16",
        "name": "VCC",
        "type": "power_in",
        "description": "Positive supply voltage, 2 V to 5.5 V (absolute maximum 7 V). Decouple locally with a 0.1 uF ceramic capacitor to GND."
      }
    ],
    "provenance": {
      "extractor": "ds2sf",
      "datasheet": {
        "url": "https://www.ti.com/lit/ds/symlink/sn74lv595a.pdf",
        "pages": 37,
        "sha256": "191b0e955c531d56",
        "source_tier": "mfr"
      },
      "cad": "KiCad official (CC-BY-SA 4.0)",
      "pins": {
        "total": 16,
        "described": 16,
        "cites_pages": true,
        "refuses_to_fabricate": true
      }
    },
    "viewers": {
      "symbol": "viewers/symbol.html",
      "footprint": "viewers/footprint.html"
    },
    "pin1": {
      "pad": "1",
      "at": [
        -2.8625,
        -2.275
      ],
      "corner": "top-left",
      "source": "silk-marker",
      "derived_from": "TSSOP-16_4.4x5mm_P0.65mm@sha256:fbac79fc5f310754",
      "mark": "drawn"
    },
    "logic": {
      "family_id": "74LV595",
      "logic_family": "74LV",
      "function_code": "595",
      "function_class": "ShiftRegister",
      "function_name": "8-Bit SIPO Shift Register with Output Latch",
      "manufacturer": "Texas Instruments",
      "is_specialty": false
    },
    "models_3d": [
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        "file": "sn74lv595apwr.step",
        "role": "plain",
        "up": "Z",
        "units": "mm",
        "origin": "footprint origin = pad-pattern centre",
        "seat": "z = 0",
        "extents_mm": [
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        ],
        "zmin_mm": 0,
        "centre_offset_mm": 0,
        "footprint_binding": "identity",
        "sha256": "6ad5e98224d02a427d9a6b929a28dbc158b9925fba5adec12db05079f1016948",
        "checked": "2026-10-07",
        "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"
      },
      {
        "file": "sn74lv595apwr-etched.step",
        "role": "eda",
        "up": "Z",
        "units": "mm",
        "origin": "footprint origin = pad-pattern centre",
        "seat": "z = 0",
        "extents_mm": [
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        "zmin_mm": 0,
        "centre_offset_mm": 0,
        "footprint_binding": "identity",
        "sha256": "f0bfe642b697da598f0fd24f30ad63975e59726c06c04b3f430c8d6f1719ca37",
        "checked": "2026-10-19",
        "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"
      }
    ]
  },
  "metadata": {
    "specs": {
      "Manufacturer": "Texas Instruments",
      "Package": "TSSOP-16",
      "Category": "Logic",
      "Pins": "16"
    }
  },
  "sections": [
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    "viewers",
    "readme",
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  "discovery_triggers": [
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  "discovery_pitch": "SN74LV595APWR (Texas Instruments) component page with datasheet-verified CAD.",
  "author": {
    "name": "Ray"
  },
  "dependencies": {},
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    "path": "docs/hero.png"
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  "visibility": {
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  "variants": [
    {
      "mpn": "SN74LV595APWR",
      "kind": "packaging"
    },
    {
      "mpn": "SN74LV595APWRD",
      "kind": "packaging"
    },
    {
      "mpn": "SN74LV595APWRDR",
      "kind": "packaging"
    },
    {
      "mpn": "SN74LV595APWRNS",
      "kind": "packaging"
    },
    {
      "mpn": "SN74LV595APWRNSR",
      "kind": "packaging"
    },
    {
      "mpn": "SN74LV595APWRRGY",
      "kind": "packaging"
    },
    {
      "mpn": "SN74LV595APWRRGYR",
      "kind": "packaging"
    },
    {
      "mpn": "SN74LV595APWRBQB",
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  "updated_at": "2026-09-25T07:26:07.545Z"
}