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SN74LV595ADR
Public Made by Adomby adom
Texas Instruments Shift Registers, SOIC-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownSN74LV595ADR
Texas Instruments · Shift Registers · SOIC-16
SN74LV595ADR from Texas Instruments, in a SOIC-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | QB | tri_state | Parallel 3-state output (bit 1) from 8-bit storage register, HIGH-impedance when OE=HIGH. |
| 2 | QC | tri_state | Parallel 3-state output (bit 2) from 8-bit storage register, HIGH-impedance when OE=HIGH. |
| 3 | QD | tri_state | Parallel 3-state output (bit 3) from 8-bit storage register, HIGH-impedance when OE=HIGH. |
| 4 | QE | tri_state | Parallel 3-state output (bit 4) from 8-bit storage register, HIGH-impedance when OE=HIGH. |
| 5 | QF | tri_state | Parallel 3-state output (bit 5) from 8-bit storage register, HIGH-impedance when OE=HIGH. |
| 6 | QG | tri_state | Parallel 3-state output (bit 6) from 8-bit storage register, HIGH-impedance when OE=HIGH. |
| 7 | QH | tri_state | Parallel 3-state output (bit 7) from 8-bit storage register, HIGH-impedance when OE=HIGH. |
| 8 | GND | power_in | Ground (0V) reference connection. |
| 9 | QH' | output | Serial output from shift register for cascading; remains active regardless of OE state. |
| 10 | SRCLR | input | Shift register asynchronous clear input (active LOW); clears all stages when held LOW. |
| 11 | SRCLK | input | Shift register clock input (positive-edge triggered) for serial data shifting. |
| 12 | RCLK | input | Storage register latch clock (positive-edge triggered) capturing shift register data to QA-QH. |
| 13 | OE | input | Output enable control (active LOW); places QA-QH outputs in HIGH-impedance state when HIGH. |
| 14 | SER | input | Serial data input to shift register; sampled on SRCLK rising edge. |
| 15 | QA | tri_state | Parallel 3-state output (bit 0) from 8-bit storage register, HIGH-impedance when OE=HIGH. |
| 16 | VCC | power_out | Supply voltage input (2.0V to 5.5V) for device operation. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | SOIC-16 |
| Category | Logic |
| Pins | 16 |
CAD (KiCad official)
- Symbol:
SN74LV595ADR - Footprint:
Package_SO:SOIC-16_3.9x9.9mm_P1.27mm - 3D model: SOIC-16 (KiCad packages3D, STEP)
- 3D model files:
sn74lv595adr-etched.step/sn74lv595adr-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);sn74lv595adr.step/sn74lv595adr.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (39 pp, sha256
87f5b78a7a0fe79e, retrieved 2026-09-24, tier: manufacturer) - Extractor: parts-factory
2.0.0/extract_pins 0.2, primaryclaude-haiku-4-5-20251001(text), consensusclaude-sonnet-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).