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Contents

Pinout
Key specifications
CAD (KiCad official)
Provenance

README

markdown

SN74LV574APWR

Texas Instruments · Flip Flops · TSSOP-20

SN74LV574APWR from Texas Instruments, in a TSSOP-20. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	OE	input	Active-low control pin that the pin table describes as 'Clear all channels, active low'.
2	1D	input	Channel 1 data input, sampled into its flip-flop on the positive transition of CLK.
3	2D	input	Channel 2 data input, sampled into its flip-flop on the positive transition of CLK.
4	3D	input	Channel 3 data input, sampled into its flip-flop on the positive transition of CLK.
5	4D	input	Channel 4 data input, sampled into its flip-flop on the positive transition of CLK.
6	5D	input	Channel 5 data input, sampled into its flip-flop on the positive transition of CLK.
7	6D	input	Channel 6 data input, sampled into its flip-flop on the positive transition of CLK.
8	7D	input	Channel 7 data input, sampled into its flip-flop on the positive transition of CLK.
9	8D	input	Channel 8 data input, sampled into its flip-flop on the positive transition of CLK.
10	GND	power_in	Ground reference pin.
11	CLK	input	Clock input; the Q outputs take the logic levels present on the D inputs on its positive transition.
12	8Q	tri_state	Channel 8 3-state output, designed for driving highly capacitive or relatively low-impedance loads.
13	7Q	tri_state	Channel 7 3-state output, designed for driving highly capacitive or relatively low-impedance loads.
14	6Q	tri_state	Channel 6 3-state output, designed for driving highly capacitive or relatively low-impedance loads.
15	5Q	tri_state	Channel 5 3-state output, designed for driving highly capacitive or relatively low-impedance loads.
16	4Q	tri_state	Channel 4 3-state output, designed for driving highly capacitive or relatively low-impedance loads.
17	3Q	tri_state	Channel 3 3-state output, designed for driving highly capacitive or relatively low-impedance loads.
18	2Q	tri_state	Channel 2 3-state output, designed for driving highly capacitive or relatively low-impedance loads.
19	1Q	tri_state	Channel 1 3-state output, designed for driving highly capacitive or relatively low-impedance loads.
20	VCC	power_in	Supply pin; the device operates from 2 V to 5.5 V VCC.

Key specifications

Parameter	Value
Manufacturer	Texas Instruments
Package	TSSOP-20
Category	Logic
Pins	20

CAD (KiCad official)

Symbol: SN74LV574APWR
Footprint: Package_SO:TSSOP-20_4.4x6.5mm_P0.65mm
3D model: TSSOP-20 (KiCad packages3D, STEP)
3D model files: sn74lv574apwr-etched.step / sn74lv574apwr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); sn74lv574apwr.step / sn74lv574apwr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Texas Instruments datasheet (33 pp, sha256 ebf402f3f43ded40, retrieved 2026-10-11, tier: manufacturer)
Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF