Overview Files Discover Packages Releases Dependencies Issues Breadcrumbs Pull Requests Activity

3D Model

Open in new tab ↗

Loads on click. Unloads only if this page sits in the background.

Symbol & Footprint

Schematic Symbol

Open full view ↗

Loads on click. Unloads only if this page sits in the background.

PCB Footprint

Open full view ↗

Loads on click. Unloads only if this page sits in the background.

Datasheet

Open in new tab ↗

Loads on click. Unloads only if this page sits in the background.

Download PDF

Contents

Pinout
Key specifications
CAD (KiCad official)
Provenance

README

markdown

SN74LV573ATPWR

Texas Instruments · Latches · TSSOP-20

SN74LV573ATPWR from Texas Instruments, in a TSSOP-20. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	OE	input	Active-low output-enable input; Q outputs are in normal logic state when OE is low and high-impedance state when OE is high.
2	1D	input	First data input; latched to Q output when LE transitions low.
3	2D	input	Second data input; latched to Q output when LE transitions low.
4	3D	input	Third data input; latched to Q output when LE transitions low.
5	4D	input	Fourth data input; latched to Q output when LE transitions low.
6	5D	input	Fifth data input; latched to Q output when LE transitions low.
7	6D	input	Sixth data input; latched to Q output when LE transitions low.
8	7D	input	Seventh data input; latched to Q output when LE transitions low.
9	8D	input	Eighth data input; latched to Q output when LE transitions low.
10	GND	power_in	Ground reference.
11	LE	input	Active-high latch-enable input; Q outputs follow D inputs when LE is high, held when LE is low.
12	8Q	tri_state	Eighth data output (IOL = 16 mA, IOH = -16 mA); follows 8D when LE is high, held when LE is low, high-impedance when OE is high.
13	7Q	tri_state	Seventh data output (IOL = 16 mA, IOH = -16 mA); follows 7D when LE is high, held when LE is low, high-impedance when OE is high.
14	6Q	tri_state	Sixth data output (IOL = 16 mA, IOH = -16 mA); follows 6D when LE is high, held when LE is low, high-impedance when OE is high.
15	5Q	tri_state	Fifth data output (IOL = 16 mA, IOH = -16 mA); follows 5D when LE is high, held when LE is low, high-impedance when OE is high.
16	4Q	tri_state	Fourth data output (IOL = 16 mA, IOH = -16 mA); follows 4D when LE is high, held when LE is low, high-impedance when OE is high.
17	3Q	tri_state	Third data output (IOL = 16 mA, IOH = -16 mA); follows 3D when LE is high, held when LE is low, high-impedance when OE is high.
18	2Q	tri_state	Second data output (IOL = 16 mA, IOH = -16 mA); follows 2D when LE is high, held when LE is low, high-impedance when OE is high.
19	1Q	tri_state	First data output (IOL = 16 mA, IOH = -16 mA); follows 1D when LE is high, held when LE is low, high-impedance when OE is high.
20	VCC	power_in	Power supply voltage, 4.5 V to 5.5 V recommended operating range.

Key specifications

Parameter	Value
Manufacturer	Texas Instruments
Package	TSSOP-20
Category	Logic
Pins	20

CAD (KiCad official)

Symbol: SN74LV573ATPWR
Footprint: Package_SO:TSSOP-20_4.4x6.5mm_P0.65mm
3D model: TSSOP-20 (KiCad packages3D, STEP)
3D model files: sn74lv573atpwr-etched.step / sn74lv573atpwr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); sn74lv573atpwr.step / sn74lv573atpwr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Texas Instruments datasheet (16 pp, sha256 90c2475d7883355b, retrieved 2026-09-22, tier: manufacturer)
Extractor: parts-factory 2.0.0 / extract_pins 0.2, primary claude-haiku-4-5-20251001 (text), consensus claude-sonnet-4-6 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF