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Contents

README

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SN74LV573APWR

Texas Instruments · Latches · TSSOP-20

SN74LV573APWR from Texas Instruments, in a TSSOP-20. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 OE input Output enable input (active low); when low, outputs are enabled and driven; when high, outputs are in high-impedance state.
2 1D input Data input 1; when LE is high, output 1Q follows this input; when LE transitions low, 1Q is latched.
3 2D input Data input 2; when LE is high, output 2Q follows this input; when LE transitions low, 2Q is latched.
4 3D input Data input 3; when LE is high, output 3Q follows this input; when LE transitions low, 3Q is latched.
5 4D input Data input 4; when LE is high, output 4Q follows this input; when LE transitions low, 4Q is latched.
6 5D input Data input 5; when LE is high, output 5Q follows this input; when LE transitions low, 5Q is latched.
7 6D input Data input 6; when LE is high, output 6Q follows this input; when LE transitions low, 6Q is latched.
8 7D input Data input 7; when LE is high, output 7Q follows this input; when LE transitions low, 7Q is latched.
9 8D input Data input 8; when LE is high, output 8Q follows this input; when LE transitions low, 8Q is latched.
10 GND power_in Ground reference, 0 V; current rating ±70 mA maximum through VCC or GND.
11 LE input Latch enable input (active high); when high, Q outputs follow D inputs; when low, Q outputs are latched at previous state.
12 8Q tri_state Data output 8, three-state; driven to logic state by latch 8 when OE is low, high-impedance when OE is high.
13 7Q tri_state Data output 7, three-state; driven to logic state by latch 7 when OE is low, high-impedance when OE is high.
14 6Q tri_state Data output 6, three-state; driven to logic state by latch 6 when OE is low, high-impedance when OE is high.
15 5Q tri_state Data output 5, three-state; driven to logic state by latch 5 when OE is low, high-impedance when OE is high.
16 4Q tri_state Data output 4, three-state; driven to logic state by latch 4 when OE is low, high-impedance when OE is high.
17 3Q tri_state Data output 3, three-state; driven to logic state by latch 3 when OE is low, high-impedance when OE is high.
18 2Q tri_state Data output 2, three-state; driven to logic state by latch 2 when OE is low, high-impedance when OE is high.
19 1Q tri_state Data output 1, three-state; driven to logic state by latch 1 when OE is low, high-impedance when OE is high.
20 VCC power_in Power supply; operating range 2 V to 5.5 V, absolute maximum -0.5 V to 7 V.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package TSSOP-20
Category Logic
Pins 20

CAD (KiCad official)

  • Symbol: SN74LV573APWR
  • Footprint: Package_SO:TSSOP-20_4.4x6.5mm_P0.65mm
  • 3D model: TSSOP-20 (KiCad packages3D, STEP)
  • 3D model files: sn74lv573apwr-etched.step / sn74lv573apwr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); sn74lv573apwr.step / sn74lv573apwr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (30 pp, sha256 6c2289095b963d29, retrieved 2026-10-01, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-4-5-20251001 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF