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SN74LV573ADBR

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Texas Instruments Latches, SSOP-20-208mil. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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SN74LV573ADBR

Texas Instruments · Latches · SSOP-20-208mil

SN74LV573ADBR from Texas Instruments, in a SSOP-20-208mil. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 OE input Output enable input; when high, the eight Q outputs are forced to high impedance, and OE should be tied to VCC through a pullup resistor to keep the outputs high-impedance during power up and power down.
2 1D input Data input for latch channel 1; Q follows D while LE is high and is held when LE is taken low.
3 2D input Data input for latch channel 2; Q follows D while LE is high and is held when LE is taken low.
4 3D input Data input for latch channel 3; Q follows D while LE is high and is held when LE is taken low.
5 4D input Data input for latch channel 4; Q follows D while LE is high and is held when LE is taken low.
6 5D input Data input for latch channel 5; Q follows D while LE is high and is held when LE is taken low.
7 6D input Data input for latch channel 6; Q follows D while LE is high and is held when LE is taken low.
8 7D input Data input for latch channel 7; Q follows D while LE is high and is held when LE is taken low.
9 8D input Data input for latch channel 8; Q follows D while LE is high and is held when LE is taken low.
10 GND power_in Ground reference pin for the device.
11 LE input Latch enable input; while high the Q outputs follow D, and when taken low the Q outputs latch the logic levels present at D.
12 8Q output Latched output for channel 8; placed in high impedance when OE is high.
13 7Q output Latched output for channel 7; placed in high impedance when OE is high.
14 6Q output Latched output for channel 6; placed in high impedance when OE is high.
15 5Q output Latched output for channel 5; placed in high impedance when OE is high.
16 4Q output Latched output for channel 4; placed in high impedance when OE is high.
17 3Q output Latched output for channel 3; placed in high impedance when OE is high.
18 2Q output Latched output for channel 2; placed in high impedance when OE is high.
19 1Q output Latched output for channel 1; placed in high impedance when OE is high.
20 VCC power_in Supply pin; the recommended operating supply range is 2 V to 5.5 V.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package SSOP-20-208mil
Category Logic
Pins 20

CAD (KiCad official)

  • Symbol: SN74LV573ADBR
  • Footprint: Package_SO:SSOP-20_5.3x7.2mm_P0.65mm
  • 3D model: SSOP-20-208mil (KiCad packages3D, STEP)
  • 3D model files: sn74lv573adbr-etched.step / sn74lv573adbr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); sn74lv573adbr.step / sn74lv573adbr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (30 pp, sha256 7ceaefb650ae906a, retrieved 2026-10-11, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF