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SN74LV540APWR
Public Made by Adomby adom
Texas Instruments Buffers, Drivers, Receivers, Transceivers, TSSOP-20. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownSN74LV540APWR
Texas Instruments · Buffers, Drivers, Receivers, Transceivers · TSSOP-20
SN74LV540APWR from Texas Instruments, in a TSSOP-20. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | OE1 | input | Active-low output enable for all Y outputs; outputs in high-impedance state when high. |
| 2 | A1 | input | Data input A1 for buffer/driver to Y1 output. |
| 3 | A2 | input | Data input A2 for buffer/driver to Y2 output. |
| 4 | A3 | input | Data input A3 for buffer/driver to Y3 output. |
| 5 | A4 | input | Data input A4 for buffer/driver to Y4 output. |
| 6 | A5 | input | Data input A5 for buffer/driver to Y5 output. |
| 7 | A6 | input | Data input A6 for buffer/driver to Y6 output. |
| 8 | A7 | input | Data input A7 for buffer/driver to Y7 output. |
| 9 | A8 | input | Data input A8 for buffer/driver to Y8 output. |
| 10 | GND | power_in | Ground reference connection. |
| 11 | Y8 | tri_state | Inverted output from A8; 3-state output with high-impedance when OE1 or OE2 is high. |
| 12 | Y7 | tri_state | Inverted output from A7; 3-state output with high-impedance when OE1 or OE2 is high. |
| 13 | Y6 | tri_state | Inverted output from A6; 3-state output with high-impedance when OE1 or OE2 is high. |
| 14 | Y5 | tri_state | Inverted output from A5; 3-state output with high-impedance when OE1 or OE2 is high. |
| 15 | Y4 | tri_state | Inverted output from A4; 3-state output with high-impedance when OE1 or OE2 is high. |
| 16 | Y3 | tri_state | Inverted output from A3; 3-state output with high-impedance when OE1 or OE2 is high. |
| 17 | Y2 | tri_state | Inverted output from A2; 3-state output with high-impedance when OE1 or OE2 is high. |
| 18 | Y1 | tri_state | Inverted output from A1; 3-state output with high-impedance when OE1 or OE2 is high. |
| 19 | OE2 | input | Active-low output enable for all Y outputs; outputs in high-impedance state when high. |
| 20 | VCC | power_in | Power supply pin; operating voltage range 2V to 5.5V. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | TSSOP-20 |
| Category | Logic |
| Pins | 20 |
CAD (KiCad official)
- Symbol:
SN74LV540APWR - Footprint:
Package_SO:TSSOP-20_4.4x6.5mm_P0.65mm - 3D model: TSSOP-20 (KiCad packages3D, STEP)
- 3D model files:
sn74lv540apwr-etched.step/sn74lv540apwr-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);sn74lv540apwr.step/sn74lv540apwr.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (29 pp, sha256
c5ca547bc295e586, retrieved 2026-09-27, tier: manufacturer) - Extractor: parts-factory
2.0.0/extract_pins 0.2, primaryclaude-haiku-4-5-20251001(text), consensusclaude-sonnet-4-6(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).