main
History Download
Ray Publish 0.1.0 bf49455 11d ago

SN74LV540APW

Texas Instruments · Buffers, Drivers, Receivers, Transceivers · TSSOP-20

SN74LV540APW from Texas Instruments, in a TSSOP-20. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 OE1 input Active-low output enable 1; a high level on OE1 or OE2 forces all eight outputs into the high-impedance state.
2 A1 input Data input A1; inputs accept voltages up to 5.5 V at any valid VCC, and enabled outputs provide inverted data.
3 A2 input Data input A2; inputs accept voltages up to 5.5 V at any valid VCC, and enabled outputs provide inverted data.
4 A3 input Data input A3; inputs accept voltages up to 5.5 V at any valid VCC, and enabled outputs provide inverted data.
5 A4 input Data input A4; inputs accept voltages up to 5.5 V at any valid VCC, and enabled outputs provide inverted data.
6 A5 input Data input A5; inputs accept voltages up to 5.5 V at any valid VCC, and enabled outputs provide inverted data.
7 A6 input Data input A6; inputs accept voltages up to 5.5 V at any valid VCC, and enabled outputs provide inverted data.
8 A7 input Data input A7; inputs accept voltages up to 5.5 V at any valid VCC, and enabled outputs provide inverted data.
9 A8 input Data input A8; inputs accept voltages up to 5.5 V at any valid VCC, and enabled outputs provide inverted data.
10 GND power_in Ground pin.
11 Y8 output Data output Y8 provides inverted data when enabled and must not sink or source more than 35 mA per output (70 mA total for the part).
12 Y7 output Data output Y7 provides inverted data when enabled and must not sink or source more than 35 mA per output (70 mA total for the part).
13 Y6 output Data output Y6 provides inverted data when enabled and must not sink or source more than 35 mA per output (70 mA total for the part).
14 Y5 output Data output Y5 provides inverted data when enabled and must not sink or source more than 35 mA per output (70 mA total for the part).
15 Y4 output Data output Y4 provides inverted data when enabled and must not sink or source more than 35 mA per output (70 mA total for the part).
16 Y3 output Data output Y3 provides inverted data when enabled and must not sink or source more than 35 mA per output (70 mA total for the part).
17 Y2 output Data output Y2 provides inverted data when enabled and must not sink or source more than 35 mA per output (70 mA total for the part).
18 Y1 output Data output Y1 provides inverted data when enabled and must not sink or source more than 35 mA per output (70 mA total for the part).
19 OE2 input Active-low output enable 2; a high level on OE2 or OE1 forces all eight outputs into the high-impedance state.
20 VCC power_in Power supply pin; VCC operates from 2 V to 5.5 V, and a 0.1 µF bypass capacitor is recommended close to the pin for a single supply.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package TSSOP-20
Category Logic
Pins 20

CAD (KiCad official)

  • Symbol: SN74LV540APW
  • Footprint: Package_SO:TSSOP-20_4.4x6.5mm_P0.65mm
  • 3D model: TSSOP-20 (KiCad packages3D, STEP)
  • 3D model files: sn74lv540apw-etched.step / sn74lv540apw-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); sn74lv540apw.step / sn74lv540apw.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (29 pp, sha256 c5ca547bc295e586, retrieved 2026-10-11, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF